ISL6146_15 Datasheet, PDF (4/28 Pages) Intersil Corporation – Low Voltage OR-ing FET Controller

ISL6146
Pin Descriptions (Continued)
MSOP/
DFN
SYMBOL
DESCRIPTION
4
ISL6146B
ISL6146E
EN
Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V
4
ISL6146C
OVP
Programmable OV protection to prevent continued operation when the monitored voltage is too high. A back-to-back FET
configuration must be employed to implement the OVP capability. Range: 0V to 24V
5
GND Chip ground reference.
6
FAULT Open-drain pull-down fault indicating output with internal on-chip filtering (T_FLT). The ISL6146 fault detection circuitry pulls
down this pin to GND as it detects a fault or a disabled input (EN = ‘0’ or EN = ‘1’).
Different types of faults and their detection mechanisms are discussed in more detail on page 17. These faults include:
a. GATE is OFF (GATE < V_IN+0.2V) when enabled [this condition is not reported on the ISL6146D and ISL6146E]
b. V_IN-V_OUT > 0.57V when ON.
c. FET G-D or G-S or D-S shorts.
d. V_IN < POR_L2H
e. V_IN < V_OUT
f. Over-Temperature
Range: 0 to V_OUT
7
ADJ
Resistor programmable V_IN - V_OUT Voltage Threshold (Vth) of the High Speed Comparator. This pin is either directly
connected to VOUT or can be connected through a 5kΩ to 100kΩ resistor to GND. Allows for adjusting the voltage difference
threshold to prevent unintended turn-off of the pass FET due to normal system voltage fluctuations.
Range: 0.4 to V_OUT
8
VOUT The second sensing node for external FET control and connected to the Load side (OR-ing MOSFET Drain). This is the
common connection point for multiple paralleled supplies. V_OUT is compared to V_IN to determine when the OR-ing FET has
to be turned off. Range: 0V to 24V
PAD Thermal Pad Connect to GND
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4
FN7667.5
August 17, 2015