ISL6146_15 Datasheet, PDF (15/28 Pages) Intersil Corporation – Low Voltage OR-ing FET Controller

ISL6146
Typical Performance Curves (Continued)
VIN
GATE
VIN
VOUT
FLT
VIN - VOUT
FIGURE 39. V_IN HOT SWAPPED TO GATE WITH BIAS = 12V NO LOAD
35
30
25
20
15
10
5
0 _-1
0
1
2
3
4
5
6
7
HS COMP ADJUST V_TH (mV)
FIGURE 41. HIGH SPEED COMPARATOR OFFSET VOLTAGE
DISTRIBUTION
40
35
30
25
20
15
10
5
0
50 52 54 56 58 60 62 64 66 68
VRr (mV)
FIGURE 43. REVERSE DETECTION RISING VOLTAGE DISTRIBUTION
FIGURE 40. FAULT ASSERTING V_IN TO V_OUT > V_{FWD_FLT}
40
35
30
25
20
15
10
5
0
17
18
19
20
21
22
V_{FWD_VR} (mV)
FIGURE 42. FORWARD REGULATION VOLTAGE DISTRIBUTION
+
V_DS
0V
V_R
t_HSpd
20V
V_GATE
V_BIAS = V_IN = 12V
t_OFF
12.6V
FIGURE 44. FAST RAMP REVERSE PROTECTION TIMING DIAGRAM
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FN7667.5
August 17, 2015