ISL6146_15 Datasheet, PDF (3/28 Pages) Intersil Corporation – Low Voltage OR-ing FET Controller

Block Diagram
ISL6146
BIAS
VIN
VOUT
Q-PUMP
VDS FORWARD
+ REGULATOR
19mV
REVERSE DETECTION
GATE
FAULT DIAGNOSTIC
1. V_IN - V_OUT > 570mV
2. GATE - V_IN < 220mV (A, B, C only)
FLT
3. TEMP > +150°C
4. V_BIAS < POR (ISL6146A/B/D/E)
5. V_IN OR V_OUT < POR (ISL6146C)
6. V_IN < V_OUT
7. Gate to Drain and Gate to Source Shorts
57mV ^COMPARATOR
+
UVLO
+
8mA
EN/EN
ENABLE
ENABLE _*
ADJ
4A
+ ^{HIGH SPEED}
COMPARATOR
* Connected to BIAS on ISL6146A/B/D/E
Connected to VOUT on ISL6146C
+- _VREF
ISL6146A/B/D/E
EN
OVP
+
+- _VREF
ISL6146C
Pin Configuration
ISL6146A, ISL6146B, ISL6146D, ISL6146E
GATE 1
8 VOUT
ISL6146
(8 LD MSOP/DFN)
TOP VIEW
VIN ₂
7 _ADJ
BIAS ₃
EN ISL6146A/D
4
EN ISL6146B/E
6 _FAULT
5 GND
GATE 1
VIN ₂
ISL6146C
UVLO ³
OVP ⁴
EPAD on DFN only, connect to GND
8 VOUT
7 _ADJ
6 FAULT
5 GND
Pin Descriptions
MSOP/
DFN
1
2
3
ISL6146A
ISL6146B
ISL6146D
ISL6146E
3
ISL6146C
4
ISL6146A
ISL6146D
SYMBOL
GATE
VIN
BIAS
DESCRIPTION
Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform OR-ing function.
The GATE drive is between V_IN + 7V at V_IN = 3.3V and V_IN +12V at V_IN = 18V.
Connected to the sourcing supply side (OR-ing MOSFET source), this pin serves as the sense pin to determine the OR’d supply
voltage. The OR-ing MOSFET will be turned off when V_IN becomes lower than V_OUT by a value more than the externally set
threshold or the defaulted internal threshold. Range: 0V to 24V
Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than V_IN.
Range: 3.0 to 24V
UVLO Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0V to 24V
EN
Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ.
Range: 0V to 24V
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3
FN7667.5
August 17, 2015