ISL59920_09 Datasheet, PDF (4/15 Pages) Intersil Corporation – Triple Analog Video Delay Lines

ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications V_SP = V_SPO = +5V, V_SM = V_SMP = -5V, GAIN = 2, T_A = +25°C, exposed die plate = -5V, x2 = 5V,
R_LOAD = 150Ω on all video outputs, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX
UNIT
POWER SUPPLY CHARACTERISTICS
V+
V_SP, V_SPO Positive Supply Range
V-
V_SM, V_SMO Negative Supply Range
I_SP
Positive Supply Current (Note 3)
ISL59920
ISL59921, ISL59922
+4.5
+5.5 V
-4.5
-5.5 V
98 115 127 mA
98 125 146 mA
ISL59923
74 90 106 mA
I_SPO
Positive Output Supply Current (Note 3)
ISL59920
ISL59921, ISL59922
11.3 13 15.3 mA
11.3 13 16.3 mA
ISL59923
9.9 13 16 mA
I_SM
I_SMO
Negative Supply Current (Note 3)
Negative Output Supply Current (Note 3)
ISL59920, ISL59921, ISL59922
ISL59923
-35.45 -31 -26 mA
-15.5 -13 -11 mA
-17.5 -13 -9.5 mA
Δ^ISP
Supply Current (Note 3)
Increase in I_SP per unit step in delay per
channel
0.9
mA
I_STANDBY
Positive Supply Standby Current (Note 3)
SERIAL INTERFACE CHARACTERISTICS
Chip enable = 0V
2.6
mA
t_MAX
t_{SEN_SETUP}
Max SCLOCK Frequency
SENABLE to SCLOCK falling edge setup time.
See Figure 34.
Maximum programming clock speed
SENABLE falling edge should occur at least
t_{SEN_SETUP} ns after previous (ignored) clock
and t_{SEN_SETUP} before next (desired) clock.
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have
indeterminate effect.
10
10
MHz
ns
t_{SEN_CYCLE} Minimum Separation Between SENABLE rising If SENABLE is taken low less than 3µs after it 3
µs
edge and next SENABLE falling edge. See Figure 34. was taken high, there is a small possibility that
an offset correction will not be initiated.
NOTES:
2. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
3. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
4. Offset measurements are referred to 75Ω load as shown in Figure 1.
75Ω
VIN
VOUT
x2 -
V_OS
75Ω
FIGURE 1. V_OS MEASUREMENT CONDITIONS
4
FN6826.1
May 28, 2009