ISL59920_09 Datasheet, PDF (13/15 Pages) Intersil Corporation – Triple Analog Video Delay Lines

ISL59920, ISL59921, ISL59922, ISL59923
Offset Compensation
To counter the effects of offset, the ISL5992x incorporates an
offset compensation circuit that reduces the offset to less than
±25mV. An offset correction cycle is triggered by the rising
edge of the SENABLE pin after writing a delay word to any of
the 3 channels. The offset calibration starts about 500ns after
the SENABLE rising edge to allow the ISL5992x time to settle
(electrically and thermally) to the new delay setting. It lasts
about 2.5µs, for a total offset correction time of 3.0µs. During
calibration, the ISL5992x’s inputs are internally shorted
together (however the characteristics of the ISL5992x’s
differential input pins stay the same), and the offset of the
output stage is adjusted until it has been minimized.
In addition to automatically triggering after a delay change
(or any register write), an additional offset calibration may be
initiated at any time, such as:
• When the die temperature changes. Applying power to the
ISL5992x will cause the die temperature to quickly increase
then slowly settle over 20 to 30 seconds. Because the
ISL5992x powers-down unused delay stages (to minimize
power consumption), the die temp will also change and
settle after a delay change. Initiating an offset 20 seconds
(or longer, depending on the thermal characteristics of the
system) after power-on or a delay change will minimize the
offset in normal operation thereafter.
• When the ambient temperature changes. If you are
monitoring the temperature, initiate a calibration every time
the temperature shifts by 5 to 10 degrees. If you are not
monitoring temperature, initiate a calibration periodically, as
expected by the environment the device is in.
• After a CENABLE (Chip Enable) cycle. The CENABLE pin
may be taken low to put the ISL5992x in a low power
standby mode to conserve power when not needed. When
the CENABLE pin goes high to exit this low power mode,
the ISL5992x will recall the delay settings but it will not
recall the correct offset calibration settings, so to maintain
low offset, a write to the delay register is required after a
CENABLE cycle. Offset errors may be as large as
±200mV coming out of standby mode - recalibration is a
necessity. For best performance, initiate an additional
calibration again once the die temperature has settled (20
to 30 seconds after coming out of standby).
• After a gain change (X2 pin changes state). The systematic
offset is different for a gain of x1 vs. a gain of x2, so an
offset calibration is recommended after a gain change.
However in a typical application the gain is permanently
fixed at x1 or x2, so this is not usually a concern.
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 35:
TEST_R pulse = RED_OUT (A) with respect to GREEN_OUT (B)
TEST_G pulse = GREEN_OUT with respect to BLUE_OUT
TEST_B pulse = BLUE_OUT with respect to RED_OUT
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current
pulse is +50µA, and the output voltage goes up. When B
precedes A, the pulse is -50µA.
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
INTERNAL DAC VOLTAGE
The slice level of the internal DAC may be programmed by
writing a byte to the test register (00). Table 3 shows the
values that should be written to change the DAC slice level.
Please keep in mind when writing to the test register that the
LSB should always be zero.
Referred to the input, the DAC slice range for the ISL5992x
is cut in half for gain of 2 mode because the slicing occurs
after the x1/x2 stage output amplifier. (In the EL9115, the
slicing occurred before the amplifier so the range of the DAC
voltage was the same for either gain of 1 or gain of 2).
4 ^{INTERNAL DAC SLICING LEVEL}
000wxyz0
COMPARATORS
RED_OUT
A
TEST_R
B
GREEN_OUT
A
TEST_G
B
BLUE_OUT
A
TEST_B
B
A
B
OUTPUT
FIGURE 35. DELAY DETECTOR
13
FN6826.1
May 28, 2009