ISL59920_09 Datasheet, PDF (11/15 Pages) Intersil Corporation – Triple Analog Video Delay Lines

ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
4.0 _3.54W
3.5
3.0
2.5
θ_{JA =Q31F°NC2/0W}
2.0
1.5
1.0
0.5
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
1
2 RIN ₊
19
17
18
DELAY LINE
16
CENABLE 7
+
R_OUT 15
4 ^GIN ₊
6 B_{IN +}
9 SDATA
10 _SCLOCK
8 SENABLE
DELAY LINE
DELAY LINE
CONTROL LOGIC
+
G_{OUT 13}
+
B_{OUT 11}
X2 20
[BOTTOM PLATE]
35
C
12 14
FIGURE 33. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
Applications Information
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that provide skew compensation
between three high-speed signals. These devices
compensate for time skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable with differing electrical lengths (due to
different twist ratios) on each pair. Via their SPI interface,
these devices can be programmed to independently
compensate for the three different cable delays while
maintaining 80MHz bandwidth at their maximum setting.
There are four different variations of the ISL5992x (ISL5992x
will be used when talking about characteristics that are
common to all four devices).
PART NUMBER
ISL59920
ISL59921
ISL59922
ISL59923
TABLE 1.
MAX DELAY
(ns)
62
46.5
31
30
NOMINAL DELAY
INCREMENT
(ns)
2.0
1.5
1.0
2.0
11
FN6826.1
May 28, 2009