ISL29147_15 Datasheet, PDF (4/15 Pages) Intersil Corporation – Low Power Ambient Light and Proximity Sensor with Enhanced Infrared Rejection

ISL29147
Electrical Specifications V_DD = 3.0V, T_A = +25°C. (Continued)
PARAMETER
DESCRIPTION
LED DRIVER (IRDR PIN)
t_r
t_f
I_{IRDR_0}
I_{IRDR_1}
I_{IRDR_2}
I_{IRDR_3}
I_{IRDR_LEAK}
V_IRDR
t_PULSE
Rise Time for IRDR Sink Current
Fall time for IRDR Sink Current
IRDR Sink Current
IRDR Sink Current
IRDR Sink Current
IRDR Sink Current
IRDR Leakage Current
IRDR Pin Voltage Compliance
I_IRDR On Time Per PROX Reading
TEST CONDITION
R_LOAD = 15Ω at IRDR pin, 20% to 80%
R_LOAD = 15Ω at IRDR pin, 80% to 20%
PROX_DR = 0; V_IRDR = 0.5V
PROX_DR = 1; V_IRDR = 0.5V
PROX_DR = 2; V_IRDR = 0.5V
PROX_DR = 3; V_IRDR = 0.5V
PROX_EN = 0; V_IRDR = 3.63V
Register bit PROX_DR = 0
MIN
MAX
(Note 10) TYP (Note 10) UNITS
25
ns
15
ns
31.25
mA
62.5
mA
125
mA
250
mA
0.001
1
µA
0.50
4.3
V
90
µs
IR-LED Specifications T_A = +25°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 10)
MAX
TYP (Note 10) UNITS
V_F
IR-LED Forward Voltage
V_R
IR-LED Reverse Voltage
λ_P
IR-LED Peak Output Wavelength
Δ_λ
IR-LED Spectral Half-Width
Φ_E
IR-LED Radiant Power
I_F = 100mA
I_F = 100mA
I_F = 100mA
I_F = 100mA
1.8
V
5.5
V
855
nm
30
nm
38
mW
I²C Electrical Specifications For SCL and SDA unless otherwise noted, V_DD = 3V, T_A = +25°C (Note 8).
SYMBOL
V_I2C
PARAMETER
Supply Voltage Range for I²C Interface
TEST CONDITIONS
MIN
(Note 10)
TYP
1.7
f_SCL
SCL Clock Frequency
V_IL
SCL and SDA Input Low Voltage
V_IH
SCL and SDA Input High Voltage
1.25
V_hys
Hysteresis of Schmitt Trigger Input
0.05V_DD
V_OL
Low-level Output Voltage (open-drain) at 4mA Sink
Current
MAX
(Note 10) UNITS
3.63
V
400 kHz
0.55
V
V
V
0.4
V
I_i
Input Leakage for each SDA, SCL Pin
t_SP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
-10
10
µA
50
ns
t_AA
SCL Falling Edge to SDA Output Data Valid
C_i
Capacitance for each SDA and SCL Pin
t_HD:STA Hold Time START Condition
After this period, the first clock
600
pulse is generated
900
ns
10
pF
ns
t_LOW LOW Period of the SCL Clock
Measured at the 30% of V_DD
1300
ns
crossing
t_HIGH
t_SU:STA
t_HD:DAT
HIGH Period of the SCL Clock
Set-up Time for a START Condition
Data Hold Time
600
ns
600
ns
30
ns
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4
FN8409.3
January 6, 2015