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| ISL29044IROMZ-T7 Datasheet, PDF (4/19 Pages) Intersil Corporation – Low Power Ambient Light and Proximity Sensor with Internal IR-LED and Digital Output | |||
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ISL29044
Electrical Specifications VDD = 3.0V, TA = +25°C. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
(Note 6) TYP (Note 6) UNIT
VIL
SCL and SDA Input Low Voltage
0.55 V
VIH
SCL and SDA Input High Voltage
1.25
V
ISDA
SDA Current Sinking Capability
VOL = 0.4V
3
5
mA
IINT
INT Current Sinking Capability
VOL = 0.4V
3
5
mA
PSRRIRDR (ÎIIRDR)/(ÎVIRDR)
PROX_DR = 0; VIRDR = 0.5V to 4.3V
5.8
mA/V
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light source of the same lux
level.
8. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware.
9. For ALS applications under light-distorting glass, please see the section titled âALS Range 1 Considerationsâ on page 9.
IR-LED Specifications TA = +25°C
PARAMETER
DESCRIPTION
VF
IR-LED Forward Voltage Drop
IR
IR-LED Reverse-Bias Current
λP
IR-LED Peak Output Wavelength
Îλ
IR-LED Spectral Half-Width
ΦE
IR-LED Radiant Power
I
IR-LED Radiant Intensity (in 0.01sr) at 0°
CONDITION
IF = 200mA
IF = 100mA
VR = 5.5V
IF = 110mA
IF = 110mA
IF = 110mA
IF = 110mA
MIN
(Note 6)
MAX
TYP (Note 6)
2.0
1.8
0.061
5
858
39
30
128
UNIT
V
V
µA
nm
nm
mW
mW/sr
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C (Note 10).
PARAMETER
VI2C
fSCL
VIL
VIH
Vhys
VOL
DESCRIPTION
Supply Voltage Range for I2C Interface
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level Output Voltage (Open-drain) at 4mA Sink
Current
CONDITION
MIN
MAX
(Note 6) TYP (Note 6) UNIT
1.7
3.63 V
400 kHz
0.55 V
1.25
V
0.05VDD
V
0.4 V
Ii
Input Leakage for each SDA, SCL Pin
tSP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
-10
10 µA
50 ns
tAA
Ci
tHD:STA
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL Pin
Hold Time (Repeated) START Condition
After this period, the first clock pulse is
600
generated.
900 ns
1 pF
ns
tLOW
tHIGH
LOW Period of the SCL Clock
HIGH period of the SCL Clock
Measured at the 30% of VDD crossing.
1300
ns
600
ns
4
FN8305.0
October 30, 2012
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