ISL2671286 Datasheet, PDF (4/15 Pages) Intersil Corporation – 12-Bit, 20kSPS SAR ADC

ISL2671286
Electrical Specifications +VCC = +5V, V_REF = +5V, f_SAMPLE = 12.5kHz, f_CLK = 16 • f_SAMPLE , unless otherwise noted. Typical
values are at T_A = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
MAX
TYP
(Note 8)
UNITS
REFERENCE INPUT
REF REF Input Range
1.25
2.5
VCC + 0.05
V
REFLEAK Current Drain
CS/SHDN = VCC
-2.5
0.01
2.5
µA
DIGITAL INPUT/OUTPUT
t_CYC ≥ 640µs, f_CLK ≤ 25kHz
t_CYC = 80µs, f_CLK= 200kHz
0.06
20
µA
0.5
20
µA
Logic Family
CMOS
V_IH Input High Voltage
V_IL
Input Low Voltage
V_OH Output High Voltage
V_OL Output Low Voltage
Data Format
I_OH = 250µA
I_OL = 250µA
3
+VCC
V
0.0
0.8
V
3
+VCC
V
0.0
0.4
V
Straight Binary
I_LEAK
C_IN
I_OZ
Input DC Leakage Current
Input Capacitance
Floating-State Output Leakage
Current
-1
0.01
1
µA
9
pF
-1
0.01
1
µA
C_OUT Floating-State Output Capacitance
POWER SUPPLY REQUIREMENTS
6
pF
+VCC Power Supply Voltage
4.50
5
5.25
V
V_ANA Quiescent Current
Power Down
t_CYC ≥ 640µs, f_CLK ≤ 25kHz
t_CYC = 90µs, f_CLK= 200kHz
CS/SHDN = VCC
280
500
µA
360
600
µA
0.5
3
µA
TEMPERATURE RANGE
Specified Performance
-40
+85
°C
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
10. Applies only to +IN.
Timing Specifications At f_CLK = 200kHz , unless otherwise noted. Typical values are at T_A = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
t_SMPL Analog Input Sample Time
See operating sequence; Figure 3
1.5
2.0
CLK
Cycles
t_{SMPL (MAX)} Maximum Sampling Frequency
t_CONV Conversion Time
See operating sequence; Figure 3
20
kHz
12
CLK
Cycles
t_dDO
t_DIS
t_EN
Delay Time, DCLOCK↓ to DOUT Data Valid
Delay Time, CS/SHDN↑ to DOUT Hi-Z
Delay Time, DCLOCK↓ to DOUT Enable
See test circuits; Figure 4
See test circuits; Figure 4 (Note 11)
See test circuits; Figure 4
36
150
ns
50
ns
21
100
ns
4
FN7863.0
November 1, 2011