ISL2671286 Datasheet, PDF (13/15 Pages) Intersil Corporation – 12-Bit, 20kSPS SAR ADC

ISL2671286
and confined to certain areas of the board. This facilitates the
use of ground planes that can be separated easily. A minimum
etch technique is generally best for ground planes because it
gives the best shielding. Digital and analog ground planes should
be joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL2671286 as possible. Avoid running digital lines under the
device, as this couples noise onto the die. The analog ground
plane should be allowed to run under the ISL2671286 to avoid
noise coupling.
Power supply lines to the device should use as large a trace as
possible, to provide low impedance paths and to reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board. Clock signals should never run near analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board.
A microstrip technique is by far the best but is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground planes, while
signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with 10μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best performance from these
decoupling components, they must be placed as close as
possible to the device.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the RMS amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f_s/2), excluding DC. The ratio is
dependent on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given in Equation 1:
Signal-to-(Noise + Distortion) = (6.02 N + 1.76)dB
(EQ. 1)
Thus, for a 12-bit converter, the ratio is 74dB and for a 10-bit
converter is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of
harmonics to the fundamental. For the ISL2671286, it is defined
as shown in Equation 2:
THD(dB) = 20log -^V---²--²-----+----^V----³--²-----+----^V----⁴--²-----+----^V----⁵--²----+-----^V----⁶--²-
V₁₂
(EQ. 2)
where V₁ is the RMS amplitude of the fundamental, and V₂, V₃,
V₄, V₅, and V₆ are the RMS amplitudes of the second through the
sixth harmonic.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
RMS value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the RMS value of the
fundamental. Also referred to as Spurious Free Dynamic Range
(SFDR), the value of this specification normally is determined by
the largest harmonic in the spectrum. For ADCs in which the
harmonics are buried in the noise floor, however, SFDR is a noise
peak.
Small-Signal Bandwidth
Small-signal bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3dB
for a signal whose peak-to-peak amplitude spans no more than
10% of the full-scale input range.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between the
measured and the ideal 1 LSB change between any two adjacent
codes in the ADC.
Zero-Code Error
Zero-code error is the deviation of the first code transition
(000...000 to 000...001) from an ideal ½ LSB step.
Gain Error
Gain error is the deviation of the full-scale input (111...111) from
the ideal span (i.e., +VREF – 1LSB) after the zero code error has
been adjusted out.
Track-and-Hold Acquisition Time
Track-and-hold acquisition time is the minimum time required for
the track-and-hold amplifier to remain in track mode for its
output to reach and settle to within 0.5 LSB of the applied input
signal.
Power Supply Rejection Ratio (PSRR)
Power supply rejection ratio is the ratio of the power in the ADC
output at full-scale frequency, f, to ADC +VCC supply of frequency
f_S (Equation 3). The frequency of this input varies from 1kHz to
1MHz.
PSRR(dB) = 10log(Pf ⁄ Pfs)
(EQ. 3)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f_s in the ADC output.
13
FN7863.0
November 1, 2011