ISL2671286 Datasheet, PDF (12/15 Pages) Intersil Corporation – 12-Bit, 20kSPS SAR ADC

ISL2671286
activated. After reset is complete, a single dummy cycle lasting
one conversion must be executed to initialize the switched
capacitor track and hold. Once the dummy cycle is complete, the
ADC mode is determined by the state of CS/SHDN. At this point,
switching between dynamic and static modes is controlled by
CS/SHDN, with no delay required between states.
POWER vs THROUGHPUT RATE
The ISL2671286 power consumption is reduced slightly at lower
conversion rates. Figure 29 shows the typical power consumption
over a wide range of throughput rates.
1000
100
conversion process and frames the data transfer. The falling
edge of CS/SHDN puts the track-and-hold into hold mode and
takes the bus out of three-state. The analog input is sampled and
the conversion initiated at this point.
The conversion result from the ISL2671286 is provided on DOUT
output as a serial data stream. The bits are clocked out on the
falling of the SCLK input. The output coding is two’s complement.
Applications Information
Analog Input Filtering
A low-pass, anti-alias filter is recommended to optimize
performance, as shown in Figure 31. The capacitive input
switching currents are averaged into a net DC current by C_FILT. It
is recommended that a high-quality capacitor with low voltage
and temperature coefficients, such as C0G/NP0, be used. A
small series resistance value minimizes voltage drops across the
resistor.
10
T_A = 25°C
V_CC = +5V
V_REF = +5V
1 ^{fCLK = 16 x fSAMPLE}
0.1
1.0
10
100
SAMPLE RATE (kHz)
FIGURE 29. SUPPLY CURRENT vs SAMPLE RATE
R_FILT
I_DC
V_IN
C_FILT
+IN
ISL2671286
–IN
6 _{TA = 25°C}
V_CC = +5V
5
V_REF = +5V
f_CLK = 16 x f_SAMPLE
4
3
CSB = LOW
(GND)
2
1
0
0.1
CSB = HIGH
(V_CC)
1.0
10
100
SAMPLE RATE (kHz)
FIGURE 30. SHUTDOWN CURRENT vs SAMPLE RATE
Serial Digital Interface
The ISL2671286 communicates using a 3-wire serial interface.
DCLOCK synchronizes the data transfer, with each bit
transmitted on the falling DCLOCK edge and captured on the
rising DCLOCK edge in the receiving system. A falling CS/SHDN
initiates data transfer, as shown in Figure 3. After CS/SHDN falls,
the second DCLOCK pulse enables DOUT. After one null bit, the
A/D conversion result is output on the DOUT line. Bringing
CS/SHDN high resets the ISL2671286 for the next data
exchange.
Figure 3 shows a detailed timing diagram for the serial interface.
The serial clock provides the conversion clock and controls the
transfer of data during conversion. CS/SHDN initiates the
FIGURE 31. INPUT FILTERING
Reduced Reference Operation
The ISL2671286 exhibits good linearity and gain over a wide
range of reference voltages (see Figures 10 and 11). When
operating at low values of VREF, offset errors and noise must be
considered because of the reduced LSB size.
Input errors can have a larger impact on performance when
operating the ADC with a reduced reference voltage, since LSB
size is proportional to VREF. Figure 8 shows how the offset in
LSBs is related to reference voltage for a typical value of V_OS. For
example, a V_OS of 100µV is 0.082 LSB with a 5V reference. If
VREF is reduced to 1V, the same 100µV offset is 0.41 LSB, and it
increases to 2.05 LSB with a 0.2V reference. The offset can be
corrected digitally after conversion, or an opposing bias can be
applied to the –IN pin (within the allowable range according to
the “Electrical Specifications”).
Similarly, total input referred noise appears as a larger fraction of
an LSB when operating at reduced VREF values. Attention should
be paid to the output noise of the driving amplifier, and proper
filtering should be applied to limit the noise that aliases in the
Nyquist zone. Averaging multiple readings can improve
performance if the application conditions allow.
Grounding and Layout
The printed circuit board that houses the ISL2671286 should be
designed so that the analog and digital sections are separated
12
FN7863.0
November 1, 2011