X9523 Datasheet, PDF (3/30 Pages) Intersil Corporation – Laser Diode Control for Fiber Optic Modules

X9523
PIN ASSIGNMENT
Pin
XBGA Name
1
B3
R_H2
2
A3
R_w2
3
A4
R_L2
4
B4
V3
5
C3
V3RO
6
D3
MR
7
C4
WP
8
D4
SCL
9
E4
SDA
10
E1
Vss
11
E3
R_L1
12
E2
R_w1
13
D1
R_H1
17
B1
V2
18
A1
V2RO
19
B2
V1RO
20
14, 15,
16,
A2
C1, C2,
D2
V1 / Vcc
NC
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP 2.
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When
the V3 input is higher than the V_TRIP3 threshold voltage, V3RO makes a transition to a HIGH
level. Connect V3 to V_SS when not used.
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is
greater than V_TRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay circuitry
on this pin. The V3RO pin requires the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates
a reset cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time
t_purst after MR has returned to it’s normally LOW state. The reset time can be selected using
bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external
“pull-down” resistor.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro-
tection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Al-
so, when the Write Protection is enabled, and the device DCP Write Lock feature is active (i.e.
the DCP Write Lock bit is “1”), then no “write” (volatile or nonvolatile) operations can be per-
formedon the wiper position of any of the integrated Digitally Controlled Potentiometers
(DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protec-
tion feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for
data input and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires an
external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
Connection to end of resistor array for (the 100 Tap) DCP 1.
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When
the V2 input is greater than the V_TRIP2 threshold voltage, V2RO makes a transition to a HIGH
level. Connect V2 to V_SS when not used.
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is great-
er than V_TRIP2, and goes LOW when V2 is less than V_TRIP2. There is no power-up reset delay
circuitry on this pin. The V2RO pin requires the use of an external “pull-up” resistor.
V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active
whenever V1 / Vcc falls below V_TRIP1. V1RO becomes active on power-up and remains ac-
tive for a time t_purst after the power supply stabilizes (t_purst can be changed by varying the
POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an
external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset
(MR) input pin.
Supply Voltage.
No Connect.
3
FN8209.0
March 10, 2005