X9523 Datasheet, PDF (10/30 Pages) Intersil Corporation – Laser Diode Control for Fiber Optic Modules

X9523
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
POR1 V2OS V3OS 0 DWLK RWEL WEL _POR0
NV
NV
NV
Bit(s)
POR1
V2OS
V1OS
CS4
DWLK
RWEL
WEL
POR0
Description
Power-on Reset bit
V2 Output Status flag
V1 Output Status flag
Always set to “0” (RESERVED)
Sets the DCP Write Lock
Register Write Enable Latch bit
Write Enable Latch bit
Power-on Reset bit
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 12. CONSTAT Register Format
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro-
vides the user with a mechanism for changing and
reading the status of various parameters of the
X9523 (See Figure 12).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when
V1/Vcc is powered down, then powered back up. The
volatile bits however, will always power-up to a known
logic state “0” (irrespective of their value at power-down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9523 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT regis-
ter). If the WEL bit is not first enabled, then ANY pro-
ceeding (volatile or nonvolatile) write operation to DCPs
or the CONSTAT register, is aborted and no ACKNOWL-
EDGE is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9523 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 13).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 13).
—When the X9523 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs can-
not be changed - i.e. DCP write operations cannot be
conducted:
DWLK
0
1
DCP Write Operation Permissible
YES (Default)
NO
The factory default setting for this bit is DWLK = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
10
FN8209.0
March 10, 2005