X9523 Datasheet, PDF (12/30 Pages) Intersil Corporation – Laser Diode Control for Fiber Optic Modules

X9523
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation
READ Operation
S
Address
t
a ^Slave
S
t
Byte
r Address
o
t
p
CS7 … CS0
10 1 0 0 1 0 0
10 1 0 0 1 01
A
A
C
C
K
K
A
C
K
Data
“Dummy” Write
Figure 14. CONSTAT Register Read Command Sequence
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, t is the DCP Write Lock
(DWLK) bit, and qr are the Power-on Reset delay time
(t_PUV1RO) control bits (POR1 - POR0). This operation
is proceeded by a START and ended with a STOP bit.
Since this is a nonvolatile write cycle, it will typically
take 5ms to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this third
step (qxys t11r) then the RWEL bit is set, but the
V2OS, V3OS, POR1, POR0, and DWLK bits remain
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and the X9523 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9523 is active (HIGH) (See "WP: Write
Protection Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 14).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9523 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.
When performing a read operation on the CONSTAT
registerm, bit CS4 will always return a “0” value.
DATA PROTECTION
There are a number of levels of data protection fea-
tures designed into the X9523. Any write to the device
first requires setting of the WEL bit in the CONSTAT
register. A write to the CONSTAT register itself, further
requires the setting of the RWEL bit. DCP Write Lock
protection of the device enables the user to inhibit
writes to all the DCPs. One further level of data protec-
tion in the X9523, is incorporated in the form of the
Write Protection pin.
X9522 Write Permission Status
DWLK
(DCP Write Lock
bit status)
1
0
1
0
WP
(Write Protect pin
status)
1
1
0
0
DCP Volatile Write
Permitted
NO
YES
NO
YES
DCP Nonvolatile
Write Permitted
NO
NO
NO
YES
Write to CONSTAT Register
Permitted
Volatile Bits Nonvolatile Bits
NO
NO
NO
NO
YES
YES
YES
YES
12
FN8209.0
March 10, 2005