X9448 Datasheet, PDF (3/19 Pages) Xicor Inc. – Mixed Signal with 2-Wire Interface

X9448
PIN NAMES
Symbol
SCL
SDA
A0 - A3
V_H0 - V_H1,
V_L0 - V_L1
V_W0 - V_W1
V_NI0, V_NI1
V_OUT0, V_OUT1
WP
V+,V-
V_CC
V_SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometers (terminal equivalent)
Potentiometers (wiper equivalent)
Comparator Input Voltages
Buffered Comparator Outputs
Hardware Write Protection
Analog and Voltage Comparator
Supplies
System/Digital Supply Voltage
System Ground
No Connection
PRINCIPLES OF OPERATION
The X9448 is a highly integrated microcircuit incorpo-
rating two resistor arrays, two voltage comparators
and their associated registers and counters; and the
serial interface logic providing direct communication
between the host and the digitally-controlled potenti-
ometers and voltage comparators.
Serial Interface
The X9448 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9448 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t_LOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9448 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t_HIGH). The X9448 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9448 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9448 will respond with a final acknowledge.
Array Description
The X9448 is comprised of two resistor arrays and
two voltage comparators. Each array contains 63 dis-
crete resistive segments that are connected in series.
The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (V_H
and V_L inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V_W) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
3
FN8201.0
April 18, 2005