X9448 Datasheet, PDF (2/19 Pages) Xicor Inc. – Mixed Signal with 2-Wire Interface

X9448
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9448.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Device Address (A₀ - A₃)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9448. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins
V_H (V_H0 - V_H1), V_L (V_L0 - V_L1)
The V_H and V_L inputs are equivalent to the terminal con-
nections on either end of a mechanical potentiometer.
V_W (V_W0 - V_W1)
The wiper output is equivalent to the wiper output of a
mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input V_NI0, V_NI1
V_NI0 and V_NI1 are the input voltages to the plus (non-
inverting) inputs of the two comparators.
Buffered Voltage Outputs V_OUT0, V_OUT1
The V_OUT0, and V_OUT1 are the buffered voltage
comparator outputs enabled by respective bits in the
volatile analog control register.
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper counter and analog control registers.
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.
System Supply V_CC and Ground V_SS
The system supply V_CC and its reference V_SS is used
to bias the interface and control circuits.
PIN CONFIGURATION
V_CC
V_L0
V_H0
V_W0
A₂
WP
SDA
A1
V_L1
V_H1
V_W1
V_SS
SOIC
1
24
2
23
3
22
4
21
5
20
6
19
7 ^X9448
18
8
17
9
16
10
15
11
14
12
13
V+
V_OUT0
V_NI0
NC
A0
NC
A₃
SCL
NC
V_NI1
V_OUT1
V-
SDA
A₁
V_L1
V_H1
V_W1
V_SS
NC
V-
V_OUT1
V_NI1
SCL
A₃
TSSOP
1
24
2
23
3
22
4
21
5
20
6
19
7 ^X9448 ₁₈
8
17
9
16
10
15
11
14
12
13
WP
A₂
V_W0
V_H0
V_L0
V_CC
NC
V+
V_OUT0
V_NI0
A₀
NC
2
FN8201.0
April 18, 2005