X9409_06 Datasheet, PDF (3/20 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometers

PIN CONFIGURATION
X9409
V_CC
V_L0/R_L0
V_H0/R_H0
V_W0/R_W0
A₂
WP
SDA
A₁
V_L1/R_L1
V_H1/R_H1
V_W1/R_W1
V _SS
SOIC
1
24
2
23
3
22
4
21
5
20
6
19
7 ^X9409 18
8
17
9
16
10
15
11
14
12
13
NC
V_L3/R_L3
V_H3/R_H3
V_W3/R_W3
A₀
NC
A₃
SCL
V_L2/R_L2
V_H2/R_H2
V_W2/R_W2
NC
SDA
A₁
V_L1/R_L1
V_H1/R_H1
V_W1/R_W1
V_SS
NC
V_W2/R_W2
V_H2/R_H2
V_L2/R_L2
SCL
A₃
TSSOP
1
24
2
23
3
22
4
21
5
20
6
19
7 ^X9409 18
8
17
9
16
10
15
11
14
12
13
WP
A₂
V_W0/R_W0
V_H0/R_H0
V_L0/R_L0
V_CC
NC
V_L3/R_L3
V_H3/R_H3
V_W3/R_W3
A₀
NC
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t_LOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9409 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t_HIGH). The X9409 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9409 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9409 will respond with a final acknowledge.
Array Description
The X9409 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V_H/R_H and V_L/R_L inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V_W/R_W) output. Within each individual array only one
switch may be turned on at a time. These switches are
3
FN8192.4
October 12, 2006