X9409_06 Datasheet, PDF (2/20 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometers

X9409
Ordering Information
PART NUMBER
POTENTIOMETER
V_CC LIMITS ORGANIZATION
PART MARKING
(V)
(kΩ)
TEMP
RANGE
(°C)
PACKAGE
PKG.
DWG. #
X9409WS24I-2.7*
X9409WS G
2.7 to 5.5
10
-40 to 85 24 Ld SOIC (300 mil)
M24.3
X9409WS24IZ-2.7* (Note) X9409WS ZG
-40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027
X9409WV24-2.7
X9409WV F
0 to 70 24 Ld TSSOP (4.4mm)
MDP0044
X9409WV24Z-2.7 (Note) X9409WV ZF
0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
X9409WV24I-2.7*
X9409WV G
-40 to 85 24 Ld TSSOP (4.4mm)
MDP0044
X9409WV24IZ-2.7* (Note) X9409WV ZG
-40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9409.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Device Address (A₀ - A₃)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9409. A maximum of 16 devices may occupy the
2-wire serial bus.
V_W0/R_{W0 -} V_W3/R_W3
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
PIN NAMES
Symbol
SCL
SDA
A0-A3
V_H0/R_H0 - V_H3/R_H3,
V_L0/R_L0 - V_L3/R_L3
V_W0/R_W0 - V_W3/R_W3
WP
V_CC
V_SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pin
(terminal equivalent)
Potentiometer Pin
(wiper equivalent)
Hardware Write Protection
System Supply Voltage
System Ground (Digital)
No Connection
Potentiometer Pins
V_H0/R_H0 - V_H3/R_H3, V_L0/R_L0 - V_L3/R_L3
The V_H/R_H and V_L/R_L inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
2
FN8192.4
October 12, 2006