ISL78235 Datasheet, PDF (3/20 Pages) Intersil Corporation – 5A Automotive Synchronous Buck Regulator

Pin Configuration
ISL78235
ISL78235
(16 LD TQFN)
TOP VIEW
16 15 14 13
VIN 1
VDD 2
PG 3
SYNC 4
EPAD
12 PGND
11 PGND
10 SGND
9 FB
5
6
7
8
Pin Descriptions
PIN NUMBER
1, 16
PIN NAME
VIN
2
VDD
3
PG
4
SYNC
5
EN
6
FS
7
SS
8
COMP
9
FB
10
11, 12
13, 14, 15
Exposed Pad
SGND
PGND
PHASE
EPAD
DESCRIPTION
Input supply voltage. Place a minimum of two 22µF low ESR ceramic capacitors from VIN to PGND as close
as possible to the IC for decoupling.
Input supply voltage for the logic circuitry. A 0.1µF high frequency decoupling ceramic capacitor should also
be placed close to the VDD and SGND pin. Connect to VIN pin.
PG is an open-drain output for power-good indication. Use a 10kΩ to 100kΩ pull-up resistor connected from
PG to VIN. At power-up or EN high, PG rising edge is delayed by 1ms upon output voltage within regulation.
Mode selection pin. Connect to logic high or input voltage VIN for forced PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with a positive edge
trigger. In external synchronization the ISL78235 operates in forced PWM mode. The transition to and from
internal oscillator to external synchronization is seamless and does not require disabling of the ISL78235.
There is an internal 1MΩ pull-down resistor to SGND to prevent an undefined logic state if SYNC pin is
floating.
Regulator enable pin. Regulator is enabled when driven logic high. Regulator is shutdown and PHASE pin
discharge output capacitor when enable pin driven low.
This pin sets the internal oscillator switching frequency using a resistor, R_FS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The switching frequency is 2MHz if
FS is connected to VIN.
SS is used to adjust the soft-start time. Connect SS pin to SGND for internal 1ms soft-start time. Connect a
capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF on the SS pin.
COMP is the output of the error amplifier if COMP is not connected to VDD. An external compensation
network must be used if COMP is not tied to VDD. If COMP is tied to VDD, the error amplifier output is
internally compensated. External compensation network across COMP and SGND may be required to
improve the loop compensation of the amplifier.
The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The
output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the
output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V
reference. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the
regulator output voltage.
Signal ground, Connect to PGND.
Power ground
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω
resistor when the device is disabled. See “Functional Block Diagram” on page 2 for more detail.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias
as possible under the pad connecting to SGND plane for optimal thermal performance.
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FN8713.2
July 1, 2015