ISL78235 Datasheet, PDF (14/20 Pages) Intersil Corporation – 5A Automotive Synchronous Buck Regulator

ISL78235
Theory of Operation
The ISL78235 is a step-down switching regulator optimized for
automotive point-of-load powered applications. The regulator
operates at a default 2MHz fixed switching frequency for high
efficiency and smaller form factor while staying out of the AM
frequency band. By connecting a resistor from FS to SGND, the
operational frequency is adjustable in the range of 500kHz to
4MHz. At light load, the regulator reduces the switching
frequency by operating in Pulse Frequency Modulation (PFM)
mode, unless forced to operate in fixed frequency PWM mode, to
minimize the switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically only
45µA. The supply current is typically only 3.8µA when the
regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current, bypassing the PFM operation
at light load. The ISL78235 employs the current-mode Pulse
Width Modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. See the “Functional
Block Diagram” on page 2. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The slope
compensation is 440mV/Ts (Ts is the switching period), which
changes proportionally with frequency. The gain for the current
sensing circuit is typically 170mV/A. The control reference for the
current loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 44 shows the typical
operating waveforms during the PWM operation. The dotted lines
on V_CSA illustrate the sum of the slope compensation ramp and
the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the V_EAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and is discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
V_EAMP
V_CSA
DUTY
CYCLE
I_L
V_OUT
FIGURE 44. PWM OPERATION WAVEFORMS
SKIP Mode (PFM)
Pulling the SYNC pin low (<0.4V), forces the converter into PFM
mode. The ISL78235 enters a pulse-skipping mode at light-load
to minimize the switching loss by reducing the switching
frequency. Figure 45 on page 15 illustrates the skip mode
operation. A zero-cross sensing circuit shown in the “Functional
Block Diagram” on page 2 monitors the N-FET current for zero
crossing. When 16 consecutive cycles are detected, the regulator
enters the skip mode. During the sixteen detecting cycles, the
current in the inductor is allowed to become negative. The
counter is reset to zero when the current in any cycle does not
cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in the “Functional Block
Diagram”. Each pulse cycle is still synchronized by the PWM
clock. The P-FET is turned on at the clock's rising edge and
turned off when the output is higher than 1.2% of the nominal
regulation or when its current reaches the peak skip current limit
value. Then, the inductor current is discharging to 0A and stays at
zero (the internal clock is disabled), and the output voltage
reduces gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-FET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.2% below the nominal voltage.
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FN8713.2
July 1, 2015