ISL78235 Datasheet, PDF (17/20 Pages) Intersil Corporation – 5A Automotive Synchronous Buck Regulator

ISL78235
There is a leakage current from VIN to PHASE. It is recommended
to preload the output with 10µA minimum for accurate output
voltage. For improved loop stability performance, add 10pF to
22pF in parallel with R₂. Check loop analysis before use in
application. See “Loop Compensation Design” on page 17 for
more information.
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide a filtering
function to prevent the switching current flowing back to the
input rail. Two 22µF low ESR X7R rated ceramic capacitors in
parallel with a 0.1µF high frequency decoupling capacitor placed
very close to the VIN/VDD and SGND/PGND pins is a good
starting point for the input capacitor selection.
Loop Compensation Design
When COMP is not connected to VDD, the COMP pin is active for
external loop compensation. The ISL78235 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing circuit
in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant
and the system becomes a single order system. It is much easier
to design a type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 47 shows the small signal model of the
synchronous buck regulator.
^iin
V^in
+
^iL _LP
R_LP
ILd^ 1:D ^{Vind^}
RT
vo^
Rc
Ro
Co
d^
T _i(S)
K
Fm
+
He(S)
Tv(S)
v^comp _-Av(S)
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R₂
C₃
VFB _-
R₃
VREF
GM
+
VCOMP
R₆
C₇
C₆
FIGURE 48. TYPE II COMPENSATOR
Figure 48 shows the type II compensator and its transfer function
is expressed as Equation 5:
A_vS= ^v-ˆ---^c_vˆ---^oF---^m-_B----^p- = -_--_C-----₆----+-----_C-^G---₇--^M--_---_--^-_--^R-_R---³-₂-----+-----_R----₃----_ -_S--^--_-¹--₁---+--+---^----_{--------}^cS------_cS---^z------_p---¹-----₁--^_{---}-^---_¹--₁---+--+----^----_{-------}^c-^S-----_c--_S-^z------_p---²------_2-^----_- (EQ. 5)
Where,
_cz1 = -_R----₆--¹-_C-----₆- , _cz2 = -_R----₂--¹-_C-----₃- _cp1= _R--^C---₆-⁶--_C---+--₆--^C-_C----⁷-₇- _cp2= _C-^R----₃-²--_R--+---₂--^R-_R----³-₃-
Compensator design goal:
High DC gain
Choose Loop bandwidth f_c ~100kHz or less
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of f_c has a unity gain.
Therefore, the compensator resistance R₆ is determined by
Equation 6.
R₆ = -²---^-_G---^f--_M^c---^V---_-^o--_V--^C--_F--^o--_B--^R----^t = 13.710³  f_cV_oC_o
(EQ. 6)
Where GM is the trans-conductance, g_m, of the voltage error
amplifier and R_t is the gain of the current sense amplifier.
Compensator capacitors C₆ and C₇ are given by Equation 7.
C₆ = ^R-----_R^o---^C-₆----^o- = -^V-_I--_o-^o--_R-^C---₆--^o- ,C₇= max(^R----_R-^c---^C-₆----^o-,_----_f--_s-¹--_R-----₆-)
(EQ. 7)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 7. An optional zero can boost the phase margin. _CZ2 is
a zero due to R₂ and C₃
Put compensator zero 2 to 5 times f_c:
C₃= _----_f--_c-¹--_R-----₂-
(EQ. 8)
Submit Document Feedback ₁₇
FN8713.2
July 1, 2015