ISL78225 Datasheet, PDF (3/21 Pages) Intersil Corporation – 4-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78225
Functional Pin Descriptions (Continued)
PIN #
SYMBOL
DESCRIPTION
12
PWM_TRI
This pin enables the tri-level of the PWM output signal. Pulling this pin to GND forces the PWM output to be
traditional two level logic. Pulling the PWM_TRI pin to VCC will enable tri-level PWM signals, then the PWM output
can be at the 2.5V tri-level condition.
13, 14, 16, PWM1, PWM3, PWM2, Pulse width modulation outputs. Connect these pins to the PWM input pins of the external driver ICs. The number
17
PWM4
of active channels is determined by the state of PWM3, PWM4. For 2-phase operation, connect PWM3 to VCC;
similarly, connect PWM4 to VCC for 3-phase operation.
15
P_COM
PWM Compensation pin; connect this pin through resistor to VCC.
19
DRIVE_EN
Driver enable output pin. This pin is connected to the enable pin of MOSFET drivers.
18,20,25,
DNC
Do Not Connect – These pins must be left floating.
26,31,32
21, 22, 23, ISEN1N, ISEN1P, ISEN3N, The ISENxP and ISENxN pins are current sense inputs to individual differential amplifiers. The sensed current is
24, 27, 28, ISEN3P, ISEN2N, ISEN2P, used as a reference for current mode control and overcurrent protection. Inactive channels should have their
29, 30
ISEN4N, ISEN4P respective ISENxP pins connected to VIN and ISENxN pins left open. The ISL78225 utilizes external sense resistor
current sensing method or Inductor DCR sensing method.
33
VIN
Connect input rail to this pin. This pin is connected to the internal linear regulator, generating the power necessary
to operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 40V.
34
VCC
This pin is the output of the internal linear regulator that supplies the bias and gate voltage for the IC. A minimum
4.7µF decoupling ceramic capacitor should be connected from VCC to GND. The controller starts to operate when
the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below
the falling POR threshold. This pin can be connected directly to a +5V supply if VIN falls below 5.6V.
35
GND
Bias and reference ground for the IC.
36
MODE
Mode selection pin. Pull this pin to logic HIGH for forced PWM mode; phase dropping/adding is inactive during
forced PWM mode. Connecting a resistor from MODE pin to GND will initialize phase dropping mode (PDM). In
PDM, a 5µA fixed reference current will flow out of the MODE pin, and the phase dropping threshold can be
programmed by adjusting the resistor value.
37
IOUT
IOUT is the current monitor pin with an additional OCP adjustment function. An RC network needs to be placed
between IOUT and GND to ensure the proper operation. The voltage at the IOUT pin will be proportional to the input
current. If the voltage on the IOUT pin is higher than 2V, ISL78225 will go into overcurrent protection mode and
the chip will latch off until the EN pin is toggled.
38
VIN_SEN
The VIN_SEN pin is used for sensing the VIN voltage. A resistor divider network is connected between this pin and
boost power stage input voltage rail. When the voltage on VIN_SEN is greater than 2.4V, the VIN_OVB pin will be
pulled low to indicate an input overvoltage condition. The threshold voltage can be programmed by changing the
divider ratios.
39
VIN_OVB
The VIN_OVB pin is an open drain indicator of an overvoltage condition at the input. When the voltage on the
VIN_SEN pin is greater than the 2.4V threshold, the VIN_OVB pin will be pulled low.
40
VOUT_SEN
The VOUT_SEN pin is used for sensing the output voltage; a resistor divider network is connected between this pin
and output voltage rail. When the voltage on VOUT_SEN pin is greater than 2.4V, VOUT_OVB pin will be pulled low,
indicating an output overvoltage condition.
41
VOUT_OVB
The VOUT_OVB pin is an open drain indicator of an overvoltage condition at the output. When the voltage on the
VOUT_SEN pin is greater than the 2.4V threshold, the VOUT_OVB pin will be pulled low and latched, toggling VIN
or EN will reset the latch.
42
DMAX
DMAX pin sets the maximum duty cycle of the PWM modulator. If the DMAX pin is connected to GND, the
maximum duty cycle will be set to 91.7%. Floating this pin will limit the duty cycle to 75% and connecting the
DMAX pin to VCC will limit the duty cycle to 83.3%.
43
EN
This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to EN pin
through an appropriate resistor divider provides a means to synchronize power-up of the controller and the
MOSFET driver ICs. When EN pin is driven above 1.2V, the ISL78225 is active depending on status of the internal
POR, and pending fault states. Driving the EN pin below 1.1V will clear all fault states and the ISL78225 will
soft-start when re-enabled.
44
PGOOD
This pin is used as an indication of the end of soft-start and output regulation. It is an open-drain logic output that
is low impedance until the soft-start is completed. It will be pulled low again once the UV/OV/OC/OT conditions
are detected.
Exposed Pad
It is recommended to solder the Exposed Pad to the ground plane.
3
FN7909.0
December 15, 2011