ISL78225 Datasheet, PDF (12/21 Pages) Intersil Corporation – 4-Phase Interleaved Boost PWM Controller with Light Load Efficiency Enhancement

ISL78225
Operation Description
Multiphase Power Conversion
The technical challenges associated with producing a
single-phase converter that is both cost-effective and thermally
viable for high power applications have forced a change to the
cost-saving approach of multiphase solution. The ISL78225
controller helps reduce the complexity of implementation by
integrating vital functions and requiring minimal output
components.
Interleaving
The switching of each channel in a multiphase converter is timed
to be symmetrically out-of-phase with each of the other channels.
Take a 3-phase converter for example; each channel switches
1/3 cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has a
combined ripple frequency three times greater than the ripple
frequency of any one phase. In addition, the peak-to-peak
amplitude of the combined inductor current is reduced in
proportion to the number of phases (Equations 1 and 2). The
increased ripple frequency and the lower ripple amplitude mean
that the designer can use less per-channel inductance and lower
total input and output capacitance for any performance
specification.
Figure 13 illustrates the multiplicative effect on input ripple
current. The three channel currents (I_L1, I_L2, and I_L3) combine to
form the AC ripple current and the DC input current. The ripple
component has three times the ripple frequency of each
individual channel current. Each PWM pulse is triggered 1/3 of a
cycle after the start of the PWM pulse of the previous phase.
To understand the reduction of the ripple current amplitude in the
multiphase circuit, examine the equation representing an
individual channel’s peak-to-peak inductor current.
In Equation 1, V_IN and V_OUT are the input and the output voltages
respectively, L is the single-channel inductor value, and f_S is the
switching frequency.
I_{PP =}
-⁽--V----^O----^U---^T-----^–----V----^I--^N----⁾---V----^I--^N--
L
f_S
V
O
U
T
(EQ. 1)
The input capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression for
the peak-to-peak current after the summation of N symmetrically
phase-shifted inductor currents in Equation 2. Peak-to-peak
ripple current decreases by an amount proportional to the
number of channels. Reducing the inductor ripple current allows
the designer to use fewer or less costly input capacitors.
I_{C(P – P)}=
-⁽--V----^O----^U---^T----^–-----N------V----^I--^N----⁾---V----^I--^N--
L
f_S
V
OU
T
(EQ. 2)
IL1 + IL2 + IL3
IL3
PWM3
IL2
PWM2
IL1
PWM1
TIME
FIGURE 13. PWM AND INDUCTOR-CURRENT WAVEFORMS FOR
3-PHASE CONVERTER
PWM Operations
The timing of each channel is set by the total number of active
channels. The default channel setting for the ISL78225 is 4, and
the switching cycle is defined as the time between PWM pulse
initiation signals of each channel. The cycle time of the pulse
initiation signal is the inversion of the switching frequency set by
the resistor between the FS pin and ground. The PWM signals
command the MOSFET drivers to turn on/off the channel
MOSFETs.
In the default 4-phase operation, the PWM2 pulse starts 1/4 of a
cycle after PWM1, the PWM3 pulse starts 1/4 of a cycle after
PWM2, and the PWM4 pulse starts 1/4 of a cycle after PWM3.
Phase Selection
The ISL78225 can work in 2, 3, or 4-phase configuration.
Connecting the PWM4 to VCC selects 3-phase operation and the
pulse times are spaced in 1/3 cycle increments. Connecting the
PWM3 to VCC selects 2-phase operation and the pulse times are
spaced in 1/2 cycle increments. Unused current sense inputs
must be left floating.
Modes of Operation
The different modes of operation will be determined by the
voltage combinations of the MODE pin and the PWM_TRI pin.
If automatic phase adding/dropping function is not needed, the
MODE pin should be tied to VCC (Logic HIGH). If higher light load
efficiency is preferred, phase adding/dropping function could be
implemented by connecting the MODE pin through a resistor to
GND. A 5µA reference current will flow out of the MODE pin to
generate corresponding V_MODE. V_MODE is used to compare with
V_IOUT to determine the phase adding/dropping level.
When PWM_TRI is tied to GND (Logic LOW), the PWM outputs will
be 2-levels (i.e., 0V and 5V). When PWM_TRI is pulled to VCC
(Logic HIGH), apart from generating the 0V and 5V PWM signals,
the PWM outputs can also generate 2.5V tri-level signal. The
external driver can identify this tri-level signal and turn off both
low side and high side output signals accordingly.
12
FN7909.0
December 15, 2011