ISL78211 Datasheet, PDF (3/35 Pages) Intersil Corporation – Automotive Single-Phase Core Regulator for IMVP-6™ CPUs

ISL78211
Functional Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28, 29,
30, 31,
32, 33, 34
35
36
37
38
39
40
SYMBOL
FDE
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
NC
BOOT
UGATE
PHASE
VSSP
LGATE
VCCP
VID0, VID1, VID2,
VID3, VID4, VID5,
VID6
VR_ON
DPRSLPVR
DPRSTP#
CLK_EN
3V3
PGOOD
DESCRIPTION
Forced diode emulation enable signal. Logic high of FDE with logic low of DPRSTP# forces
the ISL78211 to operate in diode emulation mode with an increased VW-COMP voltage
window.
Analog voltage output pin. The voltage potential on this pin indicates the power delivered to
the output.
A 147kΩ resistor to VSS sets internal current reference.
Thermal overload output indicator with open-drain output. Over-temperature pull-down
resistance is 10.
Thermistor input to VR_TT# circuit and a 60µA current source is connected internally to this
pin.
A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage. The
SOFT pin is the non-inverting input of the error amplifier.
Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A
10µA current source is connected internally to this pin.
A resistor from this pin to COMP programs the switching frequency (eg. 6.81k = 300kHz).
The output of the error amplifier.
The inverting input of the error amplifier.
The output of the differential amplifier.
Remote core voltage sense input.
Remote core voltage sense return.
The output of the droop amplifier. DROOP-VO voltage is the droop voltage.
The inverting input of the droop amplifier.
An input to the IC that reports the local output voltage.
This pin is connected to one terminal of the capacitor in the current sensing R-C network.
Power stage input voltage. It is used for input voltage feed-forward to improve the input line
transient performance.
Signal ground. Connect to controller local ground.
5V control power supply.
Not connected. Ground this pin in the practical layout.
Upper gate driver supply voltage. An internal bootstrap diode is connected to the VCCP pin.
The upper-side MOSFET gate signal.
The phase node. This pin should connect to the source of upper MOSFET.
The return path of the lower gate driver.
The lower-side MOSFET gate signal.
5V power supply for the gate driver.
VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit
(MSB).
VR enable pin. A logic high signal on this pin enables the regulator.
Deeper sleep enable signal. A logic high indicates that the microprocessor is in Deeper Sleep
Mode and also indicates a slow Vo slew rate with 41mA discharging or charging the SOFT
capacitor.
Deeper sleep slow wake up signal. A logic low signal on this pin indicates that the
microprocessor is in Deeper Sleep Mode.
Digital output for system PLL clock. Goes active 13 clock cycles after V_CORE is within 20mV
of the boot voltage.
3.3V supply voltage for CLK_EN#.
Power-good open-drain output. Needs to be pulled up externally by a 680Ω resistor to VCCP
or 1.9k to 3.3V.
3
FN7578.0
March 8, 2010