ISL78211 Datasheet, PDF (17/35 Pages) Intersil Corporation – Automotive Single-Phase Core Regulator for IMVP-6™ CPUs

ISL78211
OC
INTERNAL TO ISL6261A
1
10µA
OCSET
DROOP
VSUM
DFB
DROOP
VO
ROCSET
IPHASE
Rs
L
DCR VO
CO
ESR
1
VDIFF
VSEN
RTN
1000pF
1000pF
330pF
0~10
VCC-SENSE
VSS-SENSE
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR
CURRENT SENSING
The IMVP-6™ specification reveals the critical timing
associated with regulating the output voltage.
SLEWRATE, given in the IMVP-6™ specification,
determines the choice of the SOFT capacitor, C_SOFT,
through Equation 2:
C_SOFT
=
I _GV
SLEWRATE
(EQ. 2)
If SLEWRATE is 10mV/µs, and I_GV is typically 200µA,
C_SOFT is calculated as:
C_SOFT = 200 μA (10mV μs) = 20nF
(EQ. 3)
Choosing 0.015μF will guarantee 10mV/µs SLEWRATE at
minimum I_GV value. This choice of C_SOFT controls the
start-up slew rate as well. One should expect the output
voltage to slew to the Boot value of 1.2V at a rate given
by Equation 4:
dV_soft
dt
= ^{I ss}
C _SOFT
= ^41μA
0.015 μF
= 2.8 ^mV
μs
(EQ. 4)
Selecting Rbias
To properly bias the ISL78211, a reference current needs
to be derived by connecting a 147k, 1% tolerance
resistor from the RBIAS pin to ground. This provides a
very accurate 10µA current source from which OCSET
reference current is derived.
Caution should be used during layout. This resistor
should be placed in close proximity to the RBIAS pin and
be connected to good quality signal ground. Do not
connect any other components to this pin, as they will
negatively impact the performance. Capacitance on this
pin may create instabilities and should be avoided.
Start-up Operation - CLK_EN# and PGOOD
The ISL78211 provides a 3.3V logic output pin for
CLK_EN#. The system 3.3V voltage source connects to
the 3V3 pin, which powers internal circuitry that is solely
devoted to the CLK_EN# function. The output is a CMOS
signal with 4mA sourcing and sinking capability. CMOS
logic eliminates the need for an external pull-up resistor
on this pin, eliminating the loss on the pull-up resistor
caused by CLK_EN# being low in normal operation. This
prolongs battery run time. The 3.3V supply should be
decoupled to digital ground, not to analog ground, for
noise immunity.
At start-up, CLK_EN# remains high until 13 clock cycles
after the core voltage is within 20mV of the boot voltage.
The ISL78211 triggers an internal timer for the
IMVP6_PWRGD signal (PGOOD pin). This timer allows
PGOOD to go high approximately 7ms after CLK_EN#
goes low.
Static Mode of Operation - Processor Die
Sensing
Remote sensing enables the ISL78211 to regulate the
core voltage at a remote sensing point, which
compensates for various resistive voltage drops in the
power delivery path.
The VSEN and RTN pins of the ISL78211 are connected
to Kelvin sense leads at the die of the processor through
the processor socket. (The signal names are V_{CC_SENSE}
and V_{SS_SENSE} respectively). Processor die sensing allows
17
FN7578.0
March 8, 2010