ISL6443A Datasheet, PDF (3/19 Pages) Intersil Corporation – 300kHz Dual, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller

Block Diagram
BOOT1
UGATE1
PHASE1
VCC_5V
LGATE1
PGND
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
PGOOD SD1
GATE3
FB3
g_m*V_E
0.8V REFERENCE
+
V_E
+
-
UV
PGOOD
1400kΩ
18.5pF
FB1
180kΩ
-
16kΩ
+ _0.8V
REF
+
ERROR AMP 1
-
PWM1
+
VIN SGND
SD2
VCC_5V
POR
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
OC1
OC2
UV
PGOOD
PWM2
-
+
ISEN1
CURRENT
SAMPLE
OCSET1
-
+
CURRENT
SAMPLE
+ ^{1.7V REFERENCE}
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
-
OC1
OC2
-
+
+
VIN SYNC VCC_5V
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
SAME STATE FOR
2 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
PGND
BOOT2
UGATE2
PHASE2
VCC_5V
LGATE2
18.5pF
16kΩ
ERROR AMP 2
1400kΩ
-
+
180kΩ
VSEN2
SOFT2
-
CURRENT
+
SAMPLE
+
1.7V REFERENCE
+
SS1
0.8V
REF
ISEN2
CURRENT
SAMPLE
OCSET2