ISL6443A Datasheet, PDF (11/19 Pages) Intersil Corporation – 300kHz Dual, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller

ISL6443A
Functional Description
General Description
The ISL6443A integrates control circuits for two synchronous
buck converters and one linear controller. The two synchronous
bucks operate out-of-phase to substantially reduce the input
ripple and thus reduce the input filter requirements. The chip
has four control lines (SS1, SD1, SS2, and SD2), which provide
independent control for each of the synchronous buck outputs.
The buck PWM controllers employ a free-running frequency
of 300kHz. The current mode control scheme with an input
voltage feed-forward ramp input to the modulator provides
excellent rejection of input voltage variations and provides
simplified loop compensations.
The linear controller can drive either a PNP or PFET to provide
ultra low-dropout regulation with programmable voltages.
Internal 5V Linear Regulator (VCC_5V)
All ISL6443A functions are internally powered from an
on-chip, low dropout 5V regulator. The maximum regulator
input voltage is 24V. Bypass the regulator’s output
(VCC_5V) with a 4.7µF capacitor to ground. The dropout
voltage for this LDO is typically 600mV, so when VIN is
greater than 5.6V, VCC_5V is typically 5V. The ISL6443A
also employs an undervoltage lockout circuit that disables
both regulators when VCC_5V falls below 4.4V.
The internal LDO can source over 60mA to supply the IC,
power the low side gate drivers and charge the external boot
capacitor. When driving large FETs (especially at 300kHz
frequency), little or no regulator current may be available for
external loads.
For example, a single large FET with 15nC total gate charge
requires 15nC x 300kHz = 4.5mA. Also, at higher input
voltages with larger FETs, the power dissipation across the
internal 5V will increase. Excessive dissipation across this
regulator must be avoided to prevent the junction temperature
from rising. Larger FETs can be used with 5V ±10% input
applications. The thermal overload protection circuit will be
triggered if the VCC_5V output is short circuited. Connect
VCC_5V to V_IN for 5V ±10% input applications.
Soft-Start Operation
When soft-start is initiated, the voltage on the SS pin of the
enabled PWM channels starts to ramp gradually, due to the
5μA current sourced into the external capacitor. The output
voltage follows the soft-start voltage.
When the SS pin voltage reaches 0.8V, the output voltage of
the enabled PWM channel reaches the regulation point, and
the soft-start pin voltage continues to rise. At this point the
PGOOD and fault circuitry is enabled. This completes the
soft-start sequence. Any further rise of SS pin voltage does
not affect the output voltage. By varying the values of the
soft-start capacitors, it is possible to provide sequencing of the
main outputs at start-up. The soft-start time can be obtained
from Equation 1:
t_SOFT = 0.8V_⎝⎛ -^C5---_μ-^S---_A-^S--_⎠⎞
(EQ. 1)
VCC_5V 1V/DIV
V_OUT1 1V/DIV
SS1 1V/DIV
FIGURE 13. SOFT-START OPERATION
The soft-start capacitors can be chosen to provide start-up
tracking for the two PWM outputs. This can be achieved by
choosing the soft-start capacitors such that the soft-start
capacitor ratio equals the respective PWM output voltage
ratio. For example, if one uses PWM1 = 1.2V and PWM2 =
3.3V, then the soft-start capacitor ratio should be,
C_SS1/C_SS2 = 1.2/3.3 = 0.364. Figure 14 shows that soft-start
waveform with C_SS1 = 0.01µF and C_SS2 = 0.027µF.
V_OUT2 1V/DIV
V_OUT1 1V/DIV
FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING
START-UP
Output Voltage Programming
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to FBx pin. The output voltage
value is determined by Equation 2.
V_OUTx
=
0.8
V
⎛
⎜
⎝
R_{-----1--R---+--2--}R_{-----2-⎠⎟⎞}
(EQ. 2)
where R₁ is the top resistor of the feedback divider network
and R₂ is the resistor connected from FBx to ground.
11
FN6600.1
December 7, 2007