ISL6443A Datasheet, PDF(14/19 Page) Intersil Corporation – 300kHz Dual, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ISL6443A Datasheet, PDF (14/19 Pages) Intersil Corporation – 300kHz Dual, 180° Out-of-Phase, Step-Down PWM and Single Linear Controller

◁

CONVERTER

GM = 17.5dB

MODULATOR

FPO

R2 C1

TYPE 2 EA

GEA = 18dB

ISL6443A

rise above its set point. Care must be taken to ensure that

the feedback resistorâs current exceeds the pass transistors

leakage current over the entire temperature range.

The linear regulator output can be supplied by the output of

one of the PWMs. When using a PFET, the output of the

linear regulator will track the PWM supply after the PWM

output rises to a voltage greater than the threshold of the

PFET pass device. The voltage differential between the

PWM and the linear output will be the load current times the

rDS(ON). Figure 18 shows the linear regulator (2.5V) start-up

waveform and the PWM (3.3V) start-up waveform.

FIGURE 17. FEEDBACK LOOP COMPENSATION

The zero frequency, the amplifier high-frequency gain, and

the modulator gain are chosen to satisfy most typical

applications. The crossover frequency will appear at the

point where the modulator attenuation equals the amplifier

high frequency gain. The only task that the system designer

has to complete is to specify the output filter capacitors to

position the load main pole somewhere within one decade

lower than the amplifier zero frequency. With this type of

compensation plenty of phase margin is easily achieved due

to zero-pole pair phase âboostâ.

Conditional stability may occur only when the main load pole

is positioned too much to the left side on the frequency axis

due to excessive output filter capacitance. In this case, the

ESR zero placed within the 1.2kHz to 30kHz range gives

some additional phase âboostâ. Some phase boost can also

be achieved by connecting capacitor CZ in parallel with the

upper resistor R1 of the divider that sets the output voltage

value. Please refer to âOutput Inductor Selectionâ and

âOutput Capacitor Selectionâ on page 16 for further details.

Linear Regulator

The linear regulator controller is a transconductance

amplifier with a nominal gain of 2A/V. The N-Channel

MOSFET output device can sink a minimum of 50mA. The

reference voltage is 0.8V. With 0V differential at itâs input, the

controller sinks 21mA of current. An external PNP transistor

or PFET pass element can be used. The dominant pole for

the loop can be placed at the base of the PNP (or gate of the

PFET), as a capacitor from emitter to base (source to gate of

a PFET). Better load transient response is achieved,

however, if the dominant pole is placed at the output, with a

capacitor to ground at the output of the regulator.

Under no-load conditions, leakage currents from the pass

transistors supply the output capacitors, even when the

transistor is off. Generally this is not a problem since the

feedback resistor drains the excess charge. However,

charge may build up on the output capacitor making VLDO

VOUT2 1V/DIV

VOUT3 1V/DIV

FIGURE 18. LINEAR REGULATOR START-UP WAVEFORM

0.79 0.80 0.81 0.82 0.83 0.84 0.85

FEEDBACK VOLTAGE (V)

FIGURE 19. LINEAR CONTROLLER GAIN

Base-Drive Noise Reduction

The high-impedance base driver is susceptible to system

noise, especially when the linear regulator is lightly loaded.

Capacitively coupled switching noise or inductively coupled

EMI onto the base drive causes fluctuations in the base

current, which appear as noise on the linear regulatorâs

output. Keep the base drive traces away from the step-down

converter, and as short as possible, to minimize noise

FN6600.1

December 7, 2007

▷