ISL37231 Datasheet, PDF (3/9 Pages) Intersil Corporation – 10.3125 Gb/s Retiming Dual-Channel Transceiver

ISL37231
Pin Functions and Definitions
PIN NAME
AIN1[P,N]
GND
XTAL[P,N]
AUTX1
AURX1
EEWE
CFIG2
OSCEN
AUTX2
BIN1[P,N]
BOUT1[N,P]
BOUT2[P,N]
BIN2[N,P]
LSEN
SCL
SDA
URX
UTX
OSCMODE
PIN NUMBER
A1, A42
A2, A10, A13, A16,
A17, A20, A23, A30,
A31, A34, A37, A38,
A41, B4, B6, B7, B16,
B19, B20, B26, B27,
Exposed Pad
A3, B1
A4
A5
A6
A7
A8
A9
A11, A12
A14, A15
A18, A19
A21, A22
A24
A25
A26
A27
A28
A29
DIRECTION
DESCRIPTION
Input
High-speed differential input for on-ramp (device to cable) Channel 1, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
Ground. For proper electrical and thermal performance, each of these pads must be connected
to the PCB ground plane. For the exposed pad, 3x5 or 4x5 via pattern is recommended,
assuming 0.004" diameter vias.
Input
Output
Input
Output
Output
Output
Input
Output
Output
Input
Output
Input
Output
Input
External 33MHz crystal oscillator input/output. An external 33MHz clock source (1V CMOS logic
level) can optionally be connected XTALP, in which case XTALN must be left floating. A
differential 33MHz clock source (1V CMOS logic levels) can be input on XTALP and XTALN if
OSCMODE (pin A29) is pulled high to 1.8V.
Auxiliary UART output 1. AUTX1 can be configured via the on-chip microcontroller as either a
UART output or a GPIO pin, with either 1.8V push-pull or 3.3V tolerant open drain voltage levels.
Auxiliary UART data input 1, 1.8V powered CMOS logic tolerant to 3.3V.
EEPROM write enable open drain output. Externally pulled high to 3.3V via a ≥5kΩ resistor.
Pulled low when the ISL37231 writes to an external EEPROM device via the I²C serial interface.
Thunderbolt CONFIG2 indicator output. 1.8V powered CMOS logic. Pulled high after the
ISL37231 is powered up and stable to indicate to a Thunderbolt controller that a Thunderbolt
cable has been plugged in.
Oscillator enable. CMOS logic, 1.8V. Used as a deep-sleep state indicator. During normal
operation, OSCEN is pulled high. When entering deep-sleep mode, OSCEN is pulled low. Output
is not pulled high again until transitions are detected on the URX input pin (A27).
Auxiliary UART output 2. AUTX2 can be configured via the on-chip microcontroller as either a
UART output or a GPIO pin, with either 1.8V push-pull or 3.3V tolerant open drain voltage levels.
High-speed differential input for off-ramp (cable to device) Channel 1, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
(Note 4)
High-speed differential output for off-ramp (cable to device) Channel 1, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
High-speed differential output for off-ramp (cable to device) Channel 2, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
High-speed differential input for off-ramp (cable to device) Channel 2, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
(Note 4)
Level shift enable output. 1.8V powered CMOS logic. Pulled high to indicate an operational UART
interface to the ISL37231. When pulled low, UTX (pin A28) is set to a high impedance state.
Serial interface clock. Open drain output, externally pulled high to 3.3V via a ≥5kΩ resistor. I²C
clock, recommended clock speed is 400kHz.
Serial interface data. Open drain output, externally pulled high to 3.3V via a ≥5kΩ resistor.
Bi-directional data from/to I²C bus.
UART data input. 1.8V powered CMOS logic, but URX is 3.3V tolerant. When the ISL37231 is in
“Sleep” mode, a H to L transition on URX causes the ISL37231 to drive OSCEN high.
UART data tri-statable output. 1.8V powered CMOS logic. UTX is set to a high impedance state
when the UART interface is not in use and LSEN is pulled low. If UTX interfaces to a 3.3V powered
UART, then a level translator IC may be needed.
Oscillator mode. CMOS logic, 1.8V, internally pulled low. When OSCMODE is low, the XTALP and
XTALN input pins (A3 and B1) are configured for operation with an external crystal or with an
external single-ended clock on XTALP (XTALN must be left floating in this latter case). When
OSCMODE is pulled high, the XTALP and XTALN input pins are configured for operation with an
external differential clock.
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FN8266.1
January 25, 2013