HFA3102 Datasheet, PDF (3/6 Pages) Intersil Corporation – Dual Long-Tailed Pair Transistor Array

HFA3102
Electrical Specifications T_A = 25^oC (Continued)
SYMBOLS
PARAMETER
TEST CONDITIONS
(NOTE 2)
TEST
LEVEL
ALL GRADES
MIN TYP MAX
UNITS
dV_OS/dT
Input Offset Voltage TC
(Q₁ and Q₂, Q₄ and Q₅)
I_C = 10mA, V_CE = 3V
C
-
0.5
-
µV/^oC
I_TRENCH-
LEAKAGE
Collector-to-Collector Leakage
(Pin 6, 7, 13, and 14)
∆V_TEST = 5V
B
-
0.01
-
nA
NOTE:
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only
PSPICE Model for a Single Transistor
.Model NUHFARRY NPN
+ ( IS= 1.840E-16 XTI= 3.000E+00 EG= 1.110E+00 VAF= 7.200E+01
+ VAR= 4.500E+00 BF= 1.036E+02 ISE= 1.686E-19 NE= 1.400E+00
+ IKF= 5.400E-02 XTB= 0.000E+00 BR= 1.000E+01 ISC= 1.605E-14
+ NC= 1.800E+00 IKR= 5.400E-02 RC= 1.140E+01 CJC= 3.980E-13
+ MJC= 2.400E-01 VJC= 9.700E-01 FC= 5.000E-01 CJE= 2.400E-13
+ MJE= 5.100E-01 VJE= 8.690E-01 TR= 4.000E-09 TF= 10.51E-12
+ ITF= 3.500E-02 XTF= 2.300E+00 VTF= 3.500E+00 PTF= 0.000E+00
+ XCJC= 9.000E-01 CJS= 1.689E-13 VJS= 9.982E-01 MJS= 0.000E+00
+ RE= 1.848E+00 RB= 5.007E+01 RBM= 1.974E+00 KF= 0.000E+00
+ AF= 1.000E+00)
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