HD-15530 Datasheet, PDF (3/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder

HD-15530
Pin Description (Continued)
PIN
NUMBER
18
TYPE
NAME
I
SERIAL DATA IN
19
I
ENCODER ENABLE
20
I
SYNC SELECT
21
O SEND DATA
22
I
SEND CLOCK IN
23
I
ENCODER CLOCK
24
I
V_CC
I = Input O = Output
SECTION
DESCRIPTION
Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT
CLOCK.
Encoder A high on this pin initiates the encode cycle. (Subject to the preceeding
cycle being complete.)
Encoder Actuates a Command sync for an input high and Data sync for an input low.
Encoder An active high output which enables the external source of serial data.
Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6
output.
Encoder Input to the 6:1 divider, a frequency equal to the data rate X12 is usually
input here.
Both
V_CC is the +5V power supply pin. A 0.1µF decoupling capacitor from V_CC
(pin 24) to GROUND (pin 12) is recommended.
Encoder Operation
The Encoder requires a single clock with a frequency of
twice the desired data rate applied at the SEND CLOCK
input. An auxiliary divide by six counter is provided on chip
which can be utilized to produce the SEND CLOCK by divid-
ing the DECODER CLOCK.
The Encoder’s cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK 1 .
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high SYNC SELECT input
actuates a command sync or a low will produce a data sync
for the word 2 . When the Encoder is ready to accept data,
the SEND DATA output will go high and remain high for six-
teen ENCODER SHIFT CLOCK periods 3 . During these
sixteen periods the data should be clocked into the SERIAL
DATA input with every high-to-low transition of the
ENCODER SHIFT CLOCK so it can be sampled on the low-
to-high transition 3 - 4 . After the sync and Manchester II
coded data are transmitted through the BIPOLAR ONE and
BIPOLAR ZERO outputs, the Encoder adds on an additional
bit which is the parity for that word 5 . If ENCODER
ENABLE is held high continuously, consecutive words will be
encoded without an interframe gap. ENCODER ENABLE
must go low by time 5 as shown to prevent a consecutive
word from being encoded. At any time a low on OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low-to-high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new word.
TIMING
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
SEND DATA
SERIAL
DATA IN
BIPOLAR
ONE OUT
BIPOLAR
ZERO OUT
0
1
23 4
5
6
7
15 16 17 18 19
VALID
DON’T CARE
DON’T CARE
15 14 13 12 11 10 3 2 1 0
1ST HALF 2ND HALF 15 14 13 12 11
3
2
1
0
P
SYNC SYNC 15 14 13 12 11
3
2
1
0
P
12
3
45
FIGURE 1.
5-144