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HD-15530 Datasheet, PDF (2/12 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder | |||
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HD-15530
Block Diagrams
ENCODER
12 GND
MASTER RESET
13
SEND CLK IN
22
14 ÷ 6 OUT
÷2
÷6
VCC 24
OUTPUT
INHIBIT
16
17 BIPOLAR
CHARACTER
ONE OUT
FORMER
BIPOLAR
15 ZERO OUT
ENCODER
CLK
23
BIT
COUNTER
18 19
2
21 SERIAL
20
SYNC
SEND DATA IN
SELECT
DATA
ENCODER
ENABLE
ENCODER
SHIFT CLK
DECODER
UNIPOLAR 8
DATA IN
BIPOLAR 7
ONE IN
BIPOLAR 6
ZERO IN
TRANSITION
FINDER
DECODER 5 SYNCHRONIZER
CLK
CHARACTER
IDENTIFIER
3 TAKE
DATA
10 COMMAND/
DATA SYNC
4 SERIAL
DATA OUT
BIT
RATE
CLK
PARITY 1 VALID
CHECK WORD
MASTER 13
RESET
DECODER 11
BIT
RESET
COUNTER
9 DECODER
SHIFT
CLK
Pin Description
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TYPE
NAME
O VALID WORD
O ENCODER SHIFT
CLOCK
O TAKE DATA
O SERIAL DATA OUT
I
DECODER CLOCK
I
BIPOLAR ZERO IN
I
BIPOLAR ONE IN
I
UNLPOLAR DATA IN
O DECODER SHIFT
CLOCK
O COMMAND SYNC
I
DECODER RESET
I
GROUND
I
MASTER RESET
O ÷ 6 OUT
O BIPOLAR ZERO OUT
I
OUTPUT INHIBIT
O BIPOLAR ONE OUT
SECTION
DESCRIPTION
Decoder Output high indicates receipt of a valid word, (valid parity and no Manches-
ter errors).
Encoder Output for shifting data into the Encoder. The Encoder samples SDI on the
low-to-high transition of Encoder Shift Clock.
Decoder Output is high during receipt of data after identiï¬cation of a sync pulse and
two valid Manchester data bits.
Decoder Delivers received data in correct NRZ format.
Decoder
Input drives the transition ï¬nder, and the synchronizer which in turn
supplies the clock to the balance of the decoder, input a frequency equal to
12X the data rate.
Decoder A high input should be applied when the bus is in its negative state. This pin
must be held high when the Unipolar input is used.
Decoder A high input should be applied when the bus is in its positive state. This pin
must be held low when the Unipolar input is used.
Decoder With pin 6 high and pin 7 low, this pin enters unipolar data into the transition
ï¬nder circuit. If not used this input must be held low.
Decoder Output which delivers a frequency (DECODER CLOCK ÷ 12), synchro-
nized by the recovered serial data stream.
Decoder
Output of a high from this pin occurs during output of decoded data which
was preceded by a Command (or Status) synchronizing character. A low
output indicates a Data synchronizing character.
Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK
resets the decoder bit counting logic to a condition ready for a new word.
Both Ground Supply pin.
Both
A high on this pin clears 2:1 counters in both Encoder and Decoder, and
resets the ÷ 6 circuit.
Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.
Encoder An active low output designed to drive the zero or negative sense of a
bipolar line driver.
Encoder A low on this pin forces pin 15 and 17 high, the inactive states.
Encoder An active low output designed to drive the one or positive sense of a bipolar
line driver.
5-143
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