ISL6334A_14 Datasheet, PDF (28/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334, ISL6334A
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator. Keep a position
available for C₂, and be prepared to install a high-frequency
capacitor of between 10pF and 100pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 35
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 35 unless some performance issue is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI;
the load-current slew rate, di/dt; and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output-voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 36:
ΔV ≈ (ESL) -d---i + (ESR) ΔI
dt
(EQ. 36)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 12 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I_{C(P-P )} (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V_P-P(MAX), determines the lower limit on the
inductance, as shown in Equation 37.
L ≥ (ESR) -^⎝⎛--V-----^I-^N------^–----N------V----^O----^U----^T----^⎠⎞----V----^O----^U----^T--
f_S V_{I N} V_{P-P( M A X )}
(EQ. 37)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 38 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 39
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
L ≤ -2---N-----C-----V---^O----
(ΔI)²
ΔV_MAX – ΔI(ESR)
(EQ. 38)
L ≤ -⁽--1---.--2---5----⁾--N-----C---
(ΔI)²
ΔV_MAX – ΔI(ESR)
⎝⎛^{VIN – VO}⎠⎞
(EQ. 39)
Switching Frequency Selection
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 25, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 28. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
28
FN6482.2
February 1, 2013