ISL6334A_14 Datasheet, PDF (16/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334, ISL6334A
IL
L
R_SENSE V_OUT
C_OUT
ISL6334, ISL6334A INTERNAL CIRCUIT
R_ISEN(n)
I_n
CURRENT
SENSE
ISEN-(n)
+
-
ISEN+(n)
C_T
ISEN
=
IL
-R----S-----E----N-----S----E---
RISEN
FIGURE 5. SENSE RESISTOR IN SERIES WITH INDUCTORS
Channel-Current Balance
The sensed current I_n from each active channel is summed
together and divided by the number of active channels. The
resulting average current I_AVG provides a measure of the
total load current. Channel current balance is achieved by
comparing the sensed current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel with Intersil’s patented
current-balance method.
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The compensation network shown in Figure 6 assures that
the steady-state error in the output voltage is limited only to
the error in the reference voltage (output of the DAC) and
offset errors in the OFS current source, remote-sense and
error amplifiers. Intersil specifies the guaranteed tolerance of
the ISL6334, ISL6334A to include the combined tolerances
of each of these elements.
The sensed average current I_AVG is tied to FB internally.
This current will develop voltage drop across the resistor
between FB and VDIFF pins for droop control. ISL6334,
ISL6334A can not be used for non-droop applications.
The output of the error amplifier, V_COMP, is compared to
sawtooth waveforms to generate the PWM signals. The
PWM signals control the timing of the Intersil MOSFET
drivers and regulate the converter output to the specified
reference voltage. The internal and external circuitry, which
control voltage regulation, are illustrated in Figure 6.
EXTERNAL CIRCUIT ISL6334, ISL6334A INTERNAL CIRCUIT
R_C C_{C COMP}
R_REF
C_REF
DAC
REF
R_FB
+
V_DROOP
-
FB
VDIFF
I_AVG
+
-
V_COMP
ERROR AMPLIFIER
V_OUT+
VSEN
+
V_OUT-
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6334, ISL6334A incorporates an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
output, V_DIFF, is connected to the inverting input of the error
amplifier through an external resistor.
A digital-to-analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the eight 6-bit logic signal
(VID) into one of the discrete voltages shown in Table 2. All
VID pins have no internal pull-up current sources after t_D3.
After t_D3, each VID input offers a minimum 30µA pull-up to
an internal 2.5V source for use with open-drain outputs. The
pull-up current diminishes to zero above the logic threshold
to protect voltage-sensitive output devices. External pull-up
resistors can augment the pull-up current sources in case
leakage into the driving device is greater than 30µA.
TABLE 2. VR11 VID 8 BIT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
00000000
OFF
00000001
OFF
0 0 0 0 0 0 1 0 1.60000
0 0 0 0 0 0 1 1 1.59375
0 0 0 0 0 1 0 0 1.58750
16
FN6482.2
February 1, 2013