ISL6334A_14 Datasheet, PDF(22/31 Page) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

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ISL6334A_14 Datasheet, PDF (22/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

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ISL6334, ISL6334A

successful soft-start and a fixed delay tD5. VR_RDY will be

pulled low when an undervoltage or overvoltage condition is

detected, or the controller is disabled by a reset from

EN_PWR, EN_VTT, POR, or VID OFF-code.

Undervoltage Detection

The undervoltage threshold is set at 50% of the VID code.

When the output voltage at VSEN is below the undervoltage

threshold, VR_RDY is pulled low.

Overvoltage Protection

Regardless of the VR being enabled or not, the ISL6334,

ISL6334A overvoltage protection (OVP) circuit will be active

after its POR. The OVP thresholds are different under different

operation conditions. When VR is not enabled and during the

soft-start intervals tD1, tD2 and tD3, the OVP threshold is

1.273V. Once the controller detects valid VID input, the OVP

trip point will be changed to DAC plus 175mV.

Two actions are taken by ISL6334, ISL6334A to protect the

microprocessor load when an overvoltage condition occurs.

At the inception of an overvoltage event, all PWM outputs are

commanded low instantly (less than 20ns). This causes the

Intersil drivers to turn on the lower MOSFETs and pull the

output voltage below a level to avoid damaging the load. When

the VDIFF voltage falls below the DAC plus 75mV, PWM

signals enter a high-impedance state. The Intersil drivers

respond to the high-impedance input by turning off both upper

and lower MOSFETs. If the overvoltage condition reoccurs,

ISL6334, ISL6334A will again command the lower MOSFETs to

turn on. ISL6334, ISL6334A will continue to protect the load in

this fashion as long as the overvoltage condition occurs.

Once an overvoltage condition is detected, normal PWM

operation ceases until ISL6334, ISL6334A is reset. Cycling

the voltage on EN_PWR, EN_VTT or VCC below the

POR-falling threshold will reset the controller. Cycling the

VID codes will not reset the controller..

VR_RDY

Overcurrent Protection

ISL6334, ISL6334A has two levels of overcurrent protection.

Each phase is protected from a sustained overcurrent

condition by limiting its peak current, while the combined

phase currents are protected on an instantaneous basis.

In instantaneous protection mode, ISL6334, ISL6334A

utilizes the sensed average current IAVG to detect an

overcurrent condition. See âChannel-Current Balanceâ on

page 16 for more details on how the average current is

measured. The average current is continually compared with

a constant 105ÂµA reference current, as shown in Figure 10.

Once the average current exceeds the reference current, a

comparator triggers the converter to shutdown.

The current out of IMON pin is equal to the sensed average

current IAVG. With a resistor from IMON to GND, the voltage

at IMON will be proportional to the sensed average current

and the resistor value. The ISL6334, ISL6334A continuously

monitors the voltage at IMON pin. If the voltage at IMON pin

is higher than 1.11V, a comparator triggers the overcurrent

shutdown. By increasing the resistor between IMON and

GND, the overcurrent protection threshold can be adjusted

to be less than 105ÂµA. For example, the overcurrent

threshold for the sensed average current IAVG can be set to

95ÂµA by using a 11.8kÎ© resistor from IMON to GND.

At the beginning of overcurrent shutdown, the controller

places all PWM signals in a high-impedance state within

20ns, commanding the Intersil MOSFET driver ICs to turn off

both upper and lower MOSFETs. The system remains in this

state a period of 4096 switching cycles. If the controller is still

enabled at the end of this wait period, it will attempt a

soft-start. If the fault remains, the trip-retry cycles will

continue indefinitely (as shown in Figure 11) until either

controller is disabled or the fault is cleared. Note that the

energy delivered during trip-retry cycling is much less than

during full-load operation, so there is no thermal hazard

during this kind of operation.

OUTPUT CURRENT

50%

DAC

VDIFF

SOFT-START, FAULT

AND CONTROL LOGIC

105ÂµA

IAVG

1.11V

IMON

VID + 0.175V

FIGURE 10. VR_RDY AND PROTECTION CIRCUITRY

OUTPUT VOLTAGE

2ms/DIV

FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE.

FSW = 500kHz

FN6482.2

February 1, 2013

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