KAD5610P_14 Datasheet, PDF (27/30 Pages) Intersil Corporation – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
Equivalent Circuits (Continued)
OVDD
2mA OR
3mA
DATA
DATA
OVDD
OVDD
D[9:0]P
OVDD
OVDD
DATA
DATA
2mA OR
3mA
FIGURE 46. LVDS OUTPUTS
D[9:0]N
DATA
D[9:0]
FIGURE 47. CMOS OUTPUTS
AVDD
+
0.535V
–
VCM
FIGURE 48. VCM_OUT OUTPUT
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used
to evaluate any of the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and a
family of ADC daughtercards. This USB based platform
allows a user to quickly evaluate the ADC’s performance at a
user’s specific application frequency requirements. More
information is available at
http://www.intersil.com/converters/adc_eval_platform
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for
the analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper
plane using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep
ceramic bypass capacitors very close to device pins. Longer
traces will increase inductance, resulting in diminished
dynamic performance and accuracy. Make sure that
connections to ground are direct and low impedance. Avoid
forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
27
FN6810.2
September 10, 2009