KAD5610P_14 Datasheet, PDF (26/30 Pages) Intersil Corporation – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
ADDR
(Hex)
C0
C1
C2
C3
C4
C5
C6-FF
PARAMETER
NAME
test_io
Reserved
user_patt 1_lsb
user_patt1_msb
user_patt 2_lsb
user_patt2_msb
Reserved
TABLE 17. SPI MEMORY MAP (Continued)
BIT 7
(MSB)
BIT 6
BIT 0
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB)
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
Output Test Mode [3:0]
0 = Off
1 = Midscale
Short
2 = +FS Short
3 = -FS Short
4 = Checker
Board
5 = Reserved
6 = Reserved
7 = One/Zero
Word Toggle
8 = User Input
9-15 = Reserved
Reserved
B7
B6
B5
B4
B3
B2
B1
B0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B15
B14
B13
B12
B11
B10
B9
B8
Reserved
DEF. VALUE
(Hex)
00h
00h
00h
00h
00h
00h
INDEXED/
GLOBAL
G
G
G
G
G
G
Equivalent Circuits
AVDD
AVDD
INP
CSAMP
1.6pF
1000OΩ
FΦ1
AVDD
FΦ2
CSAMP
1.6pF
INN
FΦ2
FΦ1
TO
CHARGE
PIPELINE
ΦF 3
TO
CHARGE
PIPELINE
FΦ3
FIGURE 42. ANALOG INPUTS
INPUT
AVDD
AVDD
AVDD
75kOΩ
280OΩ
75kOΩ
AVDD
75kOΩ
75kOΩ
TO
SENSE
LOGIC
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
26
AVDD
CLKP
AVDD
11kOΩ
18kOΩ
TO
CLOCK-
PHASE
GENERATION
AVDD _11kOΩ
CLKN
18kOΩ
FIGURE 43. CLOCK INPUTS
(20k PULL-UP
ON RESETN
ONLY)
OVDD
OVDD
20k Ω
INPUT
Ω
280Ω
OVDD
TO
LOGIC
FIGURE 45. DIGITAL INPUTS
FN6810.2
September 10, 2009