KAD5610P_14 Datasheet, PDF (14/30 Pages) Intersil Corporation – Dual 10-Bit, 250/210/170/125MSPS A/D Converter

KAD5610P
Theory of Operation
Functional Description
The KAD5610P is based upon a 10-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 22). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted to
a unit of charge. Proprietary charge-domain techniques are
used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of seven and one half clock cycles.
This is evident to the user as a latency between the start of a
conversion and the data being available on the digital outputs.
The device contains two A/D converter cores with carefully
matched transfer characteristics. At start-up, each core
performs a self-calibration to minimize gain and offset errors.
The reset pin (RESETN) is initially set high at power-up and
will remain in that state until the calibration is complete. The
clock frequency should remain fixed during this time, and no
SPI communications should be attempted. Recalibration can
be initiated via the SPI port at any time after the initial
self-calibration.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage
ramps and initiates the calibration when the analog and
digital supply voltages are above a threshold. The following
conditions must be adhered to for the power-on calibration to
execute successfully:
• A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If
the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high, which
starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should be
connected to an open-drain driver with a drive strength of
less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 23. The over-range output
(OR) is set high once RESETN is pulled low, and remains in
that state until calibration is complete. The OR output returns
to normal operation at that time, so it is important that the
analog input be within the converter’s full-scale range to
observe the transition. If the input is in an over-range
condition the OR pin will stay high, and it will not be possible
to detect the end of the calibration cycle.
CLOCK
GENERATION
INP
SHA
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
INN
1.25V
+
–
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 22. ADC CORE BLOCK DIAGRAM
3-BIT
FLASH
14
FN6810.2
September 10, 2009