ISL6326 Datasheet, PDF (27/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6326
C₂
R_C ^CC
COMP
FB
C₁
R₁
R_FB
IDROOP
VDIFF
FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, R_FB is selected arbitrarily. The remaining
compensation components are then selected.
R₁
=
R_F
B
----------C----⁽---E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L---C------^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
------------------------0---.--7---5----V----^I--^N--------------------------
(2π)²f₀f_HF LCR_FBV_P-P
(EQ. 36)
R_C = -0--V-.--7--^P-5---^P-V---^⎝⎛--_I^2-_N---^π---^⎠⎞-_⎝⎛--2²----_π^f--0-f--f_H--^H---_F-^F----L--L--C--C--R---_–--^F-1---^B_⎠⎞----
C_C
=
---0---.--7---5----V----^I--^N-----^⎝⎛-2----^π----f--^H----^F--------L---C-----^–---1----^⎠⎞---
(2π)²f₀f_HF LCR_FBV_P-P
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the sawtooth
signal amplitude as described in “Electrical Specifications”
on page 7.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output voltage deviation under transient
loading, ΔV_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
in Equation 37:
ΔV ≈ (ESL) -d---i + (ESR) ΔI
dt
(EQ. 37)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I_C(P-P)(ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V_P-P(MAX), determines the lower limit on the
inductance.
27
FN9262.1
May 5, 2008