ISL6326 Datasheet, PDF (26/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6326
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
+
V_DROOP
-
FB
IDROOP
VDIFF
FIGURE 16. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6326 CIRCUIT
The feedback resistor, R_FB, has already been chosen as
outlined in “Load-Line Regulation Resistor” on page 25.
Select a target bandwidth for the compensated system, f₀.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
Case 2:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----p---p-------L----C---}
0.75 V _{I N}
C_C = _2----π----0V---.-_P-7---5_P----VR----^I-_F-^N--_B----f--₀--
---------1----------
2π LC
≤
f₀
<
2----π^----C-----(^{-1-E-----S----R-----})
R_C
=
R_F
B
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 35)
Case 3:
f₀ > _2----π----C-----₍-1-E-----S----R-----₎
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.75 V_IN (ESR)
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the sawtooth
amplitude described in Electrical Specifications on page 7.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 16). Keep
a position available for C₂, and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 35
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 35 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type-III controller, as shown in Figure 17, provides the
necessary compensation.
26
FN9262.1
May 5, 2008