ISL6326 Datasheet, PDF (20/30 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6326
t_d1 is a fixed delay with the typical value as 1.36ms. t_d3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t_d3 is about 86µs.
During t_d2 and t_d4, ISL6326 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The
second soft-start ramp time t_d2 and t_d4 can be calculated
based on Equations 15 and 16:
t_d2
=
1----.--1---x----R----_S----S--
6.25 x 25
(μs
)
(EQ. 15)
t_d4
=
(_{---V----V----I--D-----}–_{-----1---.--1----})_{--x---R-----S----S--}
6.25 x 25
(μs
)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_d2 will be 704µs and the
second soft-start ramp time t_d4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t_d5. The
typical value for t_d5 is 85µs.
V_OUT, 500mV/DIV
t_d1
t_d2
t_d3 t_d4 t_d5
EN_VTT
VR_RDY
500µs/DIV
FIGURE 8. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6326 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful
soft-start and a fixed delay t_d5. VR_RDY will be pulled low
when an undervoltage or overvoltage condition is detected,
or the controller is disabled by a reset from EN_PWR,
EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals t_d1, t_d2 and t_d3, the OVP threshold is
1.275V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC + 175mV.
Two actions are taken by the ISL6326 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (>20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC + 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both
upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326 will again command the lower
MOSFETs to turn on. The ISL6326 will continue to protect
the load in this fashion as long as the overvoltage condition
occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6326 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller..
VR_RDY
UV
50%
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
85µA
I_AVG
VDIFF
+
OV
-
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
20
FN9262.1
May 5, 2008