ISL62883HRTZ-T Datasheet, PDF (27/37 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B
TABLE 5. LAYOUT CONSIDERATION (Continued)
PIN
NAME
LAYOUT CONSIDERATION
14
ISUM- Place the current sensing circuit in general
15
ISUM+ ^{proximity of the controller.}
Place C82 very close to the controller.
Place NTC thermistors R42 next to Phase-1
inductor (L1) so it senses the inductor temperature
correctly.
Each phase of the power stage sends a pair of
VSUM+ and VSUM- signals to the controller. Run
these two signals traces in parallel fashion with
decent width (>20mil).
IMPORTANT: Sense the inductor current by routing
the sensing circuit to the inductor pads.
Route R63 and R71 to the Phase-1 side pad of
inductor L1. Route R88 to the output side pad of
inductor L1.
Route R65 and R72 to the Phase-2 side pad of
inductor L2. Route R90 to the output side pad of
inductor L2.
Route R67 and R73 to the Phase-3 side pad of
inductor L3. Route R92 to the output side pad of
inductor L3.
If possible. Route the traces on a different layer
from the inductor pad layer and use vias to
connect the traces to the center of the pads. If no
via is allowed on the pad, consider routing the
traces into the pads from the inside of the
inductor. The following drawings show the two
preferred ways of routing current sensing traces.
Inductor
Inductor
Vias
TABLE 5. LAYOUT CONSIDERATION (Continued)
PIN
NAME
LAYOUT CONSIDERATION
25
VCCP A capacitor (C22) decouples it to GND. Place it in
close proximity of the controller.
26 LGATE2 Run these two traces in parallel fashion with
27
VSSP2 ^{decent width (>30mil). Avoid any sensitive analog}
signal trace from crossing over or getting close.
Recommend routing VSSP2 to the Phase-2 low-
side MOSFET (Q5 and Q1) source pins instead of
general power ground plane for better
performance.
28 PHASE2 Run these two traces in parallel fashion with
29
UGATE2
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE2 trace to the Phase-2
high-side MOSFET (Q4 and Q10) source pins
instead of general Phase-2 node copper.
30
BOOT2 Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
31~37 VID0~6 No special consideration.
38
VR_ON No special consideration.
39 DPRSLPVR No special consideration.
40 CLK_EN# No special consideration.
Other
Phase Node Minimize phase node copper area. Don’t let the
phase node copper overlap with/getting close to
other sensitive traces. Cut the power ground plane
to avoid overlapping with phase node copper.
Other
Minimize the loop consisting of input capacitor,
high-side MOSFETs and low-side MOSFETs (e.g.:
C27, C33, Q2, Q8, Q3 and Q9).
Current-Sensing
Traces
Current-Sensing
Traces
16
VDD A capacitor (C16) decouples it to GND. Place it in
close proximity of the controller.
17
VIN A capacitor (C17) decouples it to GND. Place it in
close proximity of the controller.
18
IMON Place the filter capacitor (C21) close to the CPU.
19
BOOT1 Use decent wide trace (>30mil). Avoid any
sensitive analog signal trace from crossing over or
getting close.
20 UGATE1 Run these two traces in parallel fashion with
21
PHASE1
decent width (>30mil). Avoid any sensitive analog
signal trace from crossing over or getting close.
Recommend routing PHASE1 trace to the Phase-1
high-side MOSFET (Q2 and Q8) source pins instead
of general
Phase-1 node copper.
22
VSSP1 Run these two traces in parallel fashion with
23
LGATE1 ^{decent width (>30mil). Avoid any sensitive analog}
signal trace from crossing over or getting close.
Recommend routing VSSP1 to the Phase-1 low-
side MOSFET (Q3 and Q9) source pins instead of
general power ground plane for better
performance.
24
PWM3 No special consideration.
27
FN6891.4
June 21, 2011