ISL62883HRTZ-T Datasheet, PDF (11/37 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B
Theory of Operation
Multiphase R³â„¢ Modulator
VW
MASTER CLOCK CIRCUIT
MASTER
MASTER ^COMP
CLOCK _Vcrm
CLOCK
Phase
Sequencer
gmVo
Crm
Clock1
Clock2
Clock3
VW
Vcrs1
Crs1
VW
Vcrs2
Crs2
VW
Vcrs3
Crs3
SLAVE CIRCUIT 1
Clock1 S PWM1 ^{Phase1 L1}
Q
R
IL1
gm
SLAVE CIRCUIT 2
Clock2 S PWM2 ^{Phase2 L2}
Q
R
IL2
gm
SLAVE CIRCUIT 3
Clock3 S PWM3 ^{Phase3 L3}
Q
R
IL3
gm
Vo
Co
FIGURE 3. R³â„¢ MODULATORCIRCUIT
VW
Vcrm
COMP
Master
Clock
Clock1
PWM1
Clock2
PWM2
Clock3
PWM3
VW
Hysteretic
W indow
Vcrs2 Vcrs3 Vcrs1
FIGURE 4. R³â„¢ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
Vcrm
Master
Clock
Clock1
PWM1
Clock2
PWM2
Clock3
PWM3
VW
COMP
VW
Vcrs1
Vcrs3
Vcrs2
FIGURE 5. R³â„¢ MODULATOROPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
The ISL62883 is a multiphase regulator, which implements Intel™
IMVP-6.5™ protocol. It can be programmed for 1-, 2- or 3-phase
operation for microprocessor core applications. It uses Intersil
patented R³â„¢ (Robust Ripple Regulator™) modulator. The R³â„¢
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 3 conceptually shows the ISL62883 multiphase R³â„¢
modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C_rm with a current source equal
to g_mV_o, where g_m is a gain factor. C_rm voltage V_crm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a one-
shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the ISL62883 is in
3-phase mode, the master clock signal will be distributed to the
three phases, and the Clock1~3 signals will be 120° out-of-
phase. If the ISL62883 is in 2-phase mode, the master clock
signal will be distributed to Phases 1 and 2, and the Clock1 and
Clock2 signals will be 180° out-of-phase. If the ISL62883 is in
1-phase mode, the master clock signal will be distributed to
Phases 1 only and be the Clock1 signal.
Each slave circuit has its own ripple capacitor C_rs, whose voltage
mimics the inductor ripple current. A g_m amplifier converts the
inductor voltage into a current source to charge and discharge
C_rs. The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C_rs. When C_rs
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FN6891.4
June 21, 2011