ISL62883HRTZ-T Datasheet, PDF (12/37 Pages) Intersil Corporation – Multiphase PWM Regulator for IMVP-6.5™ Mobile CPUs

ISL62883, ISL62883B
voltage V_Crs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges C_rs.
Since the ISL62883 works with V_crs, which are large-amplitude
and noise-free synthesized signals, the ISL62883 achieves lower
phase jitter than conventional hysteretic mode and fixed PWM
mode controllers. Unlike conventional hysteretic mode
converters, the ISL62883 has an error amplifier that allows the
controller to maintain a 0.5% output voltage accuracy.
Figure 5 shows the operation principles during load insertion
response. The COMP voltage rises during load insertion,
generating the master clock signal more quickly, so the PWM
pulses turn on earlier, increasing the effective switching
frequency, which allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
falls as the VW voltage falls, reducing the current PWM pulse
width. This kind of behavior gives the ISL62883 excellent
response speed.
The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
Diode Emulation and Period Stretching
Phase
UGATE
LGATE
IL
FIGURE 6. DIODE EMULATION
ISL62883 can operate in diode emulation (DE) mode to improve
light load efficiency. In DE mode, the low-side MOSFET conducts
when the current is flowing from source to drain and doesn’t not
allow reverse current, emulating a diode. As Figure 6 shows, when
LGATE is on, the low-side MOSFET carries current, creating
negative voltage on the phase node due to the voltage drop across
the ON-resistance. The ISL62883 monitors the current through
monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
If the load current is light enough, as Figure 6 shows, the inductor
current will reach and stay at zero before the next phase node
pulse, and the regulator is in discontinuous conduction mode
(DCM). If the load current is heavy enough, the inductor current
will never reach 0A, and the regulator is in CCM although the
controller is in DE mode.
Vcrs
CCM/DCM BOUNDARY
VW
iL
Vcrs
VW ^{LIGHT DCM}
iL
Vcrs
DEEP DCM
VW
iL
FIGURE 7. PERIOD STRETCHING
Figure 7 shows the operation principle in diode emulation mode at
light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor current
triangle the same in the three cases. The ISL62883 clamps the
ripple capacitor voltage V_crs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_crs,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps increase light load efficiency.
Start-up Timing
With the controller's V_DD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the 3.3V logic
high threshold. The ISL62883 uses digital soft start to ramp up
DAC to the boot voltage of 1.1V at about 2.5mV/µs. Once the
output voltage is within 10% of the boot voltage for 13 PWM
cycles (43µs for frequency = 300kHz), CLK_EN# is pulled low and
DAC slews at 5mV/µs to the voltage set by the VID pins. PGOOD
is asserted high in approximately 7ms. Figure 8 shows the typical
start-up timing. Similar results occur if VR_ON is tied to V_DD, with
the soft-start sequence starting 120µs after V_DD crosses the
POR threshold.
VDD
VR_ON
DAC
CLK_EN#
PGOOD
5mV/µs
2.5mV/µs
90%VBOOT
800µs
VID
COMMAND
VOLTAGE
13 SWITCHING
CYCLES
~7ms
FIGURE 8. SOFT-START WAVEFORMS
12
FN6891.4
June 21, 2011