ISL6237 Datasheet, PDF (27/35 Pages) Intersil Corporation – High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Computers

ISL6237
current. After FB drops below the regulation point, the
controller turns off the low-side MOSFET (LGATE pulled low)
and triggers a constant on-time (UGATE driven high). When
the on-time has expired, the controller re-enables the
low-side MOSFET until the controller detects that the
inductor current dropped below the zero-crossing threshold.
Starting with a LGATE pulse greatly reduces the peak output
voltage when compared to starting with a UGATE pulse, as
long as VFB < VREF, LGATE is off and UGATE is on, similar
to pure SKIP mode.
Reference and Linear Regulator (REF and
LDO)
The 2V reference (REF) is accurate to ±1% over
temperature, making REF useful as a precision system
reference. Bypass REF to GND with a 0.1µF (min) capacitor.
REF can supply up to 50µA for external loads.
An internal regulator produces a fixed 5V
(LDOREFIN < 0.2V) or 3.3V (LDOREFIN > VCC - 1V). In an
adjustable mode, the LDO output can be set from 0.7V to
4.5V. The LDO output voltage is equal to two times the
LDOREFIN voltage. The LDO regulator can supply up to
100mA for external loads. Bypass LDO with a minimum
4.7µF ceramic capacitor. When the LDOREFIN < 0.2V and
BYP voltage is 5V, the LDO bootstrap-switchover to an
internal 0.7Ω P-channel MOSFET switch connects BYP to
LDO pin while simultaneously shutting down the internal
linear regulator. These actions bootstrap the device,
powering the loads from the BYP input voltages, rather than
through internal linear regulators from the battery. Similarly,
when the BYP = 3.3V and LDOREFIN = VCC, the LDO
bootstrap-switchover to an internal 1.5Ω P-Channel
MOSFET switch connects BYP to LDO pin while
simultaneously shutting down the internal linear regulator.
No switchover action in adjustable mode.
Current-Limit Circuit (ILIM_) with r_DS(ON)
Temperature Compensation
The current-limit circuit employs a "valley" current-sensing
algorithm. The ISL6237 uses the on-resistance of the
synchronous rectifier as a current-sensing element. If the
magnitude of the current-sense signal at PHASE_ is above
the current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the current-
limit threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the current-limit
threshold, inductor value and input and output voltage.
For lower power dissipation, the ISL6237 uses the
on-resistance of the synchronous rectifier as the
current-sense element. Use the worst-case maximum value
for r_DS(ON) from the MOSFET data sheet. Add some margin
for the rise in r_DS(ON) with temperature. A good general rule
is to allow 0.5% additional resistance for each °C of
temperature rise. The ISL6237 controller has a built-in 5µA
current source as shown in Figure 70. Place the hottest
power MOSFETs as close to the IC as possible for best
thermal coupling. The current limit varies with the on-
resistance of the synchronous rectifier. When combined with
the undervoltage-protection circuit, this current-limit method
is effective in almost every circumstance.
A negative current limit prevents excessive reverse inductor
currents when VOUT sinks current. The negative
current-limit threshold is set to approximately 120% of the
positive current limit and therefore tracks the positive current
limit when ILIM_ is adjusted. The current-limit threshold is
adjusted with an external resistor for ISL6237 at ILIM_. The
current-limit threshold adjustment range is from 20mV to
200mV. In the adjustable mode, the current-limit threshold
voltage is 1/10th the voltage at ILIM_. The voltage at ILIM
pin is the product of 5µA*R_ILIM. The threshold defaults to
100mV when ILIM_ is connected to VCC. The logic
threshold for switch-over to the 100mV default value is
approximately VCC - 1V.
The PC board layout guidelines should be carefully
observed to ensure that noise and DC errors do not corrupt
the current-sense signals at PHASE_.
I _PEAK
I _LOAD
ΔI
I _LOAD(MAX)
I _LIMIT
ILIM _{(VAL) = ILOAD −}
ΔI
2
TIME
FIGURE 69. “VALLEY” CURRENT LIMIT THRESHOLD POINT
ILIM_
RILIM VILIM
5µA
VCC
9R ^{TO CURRENT}
LIMIT LOGIC
R
FIGURE 70. CURRENT LIMIT BLOCK DIAGRAM
27
FN6418.4
March 18, 2008