ISL6262A Datasheet, PDF (26/28 Pages) Intersil Corporation – Two-Phase Core Controller Santa Rosa, IMVP-6+

ISL6262A
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.
In the previous example, the two errors add to 4A. For the
two phase DC/DC, the currents would be 22A in one phase
and 18A in the other phase. In the above analysis, the
current balance can be calculated with 2A/20A = 10%. This
is the worst case calculation. For example, the actual
tolerance of two 10% DCRs is 10%*sqrt(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for
better thermal management. Customer can put a resistor in
parallel with the current sensing capacitor on the phase of
interest in order to purposely increase the current in that
phase.
If the PC board trace resistance from the inductor to the
microprocessor are significantly different between two
phases, the current will not be balanced perfectly. Intersil
has a proprietary method to achieve the perfect current
sharing in case of severe unbalanced layout.
When choosing the current sense resistor, both the
tolerance of the resistance and the TCR are important. Also,
the current sense resistor’s combined tolerance at a wide
temperature range should be calculated.
Droop Using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
Figure 42 shows the equivalent circuit of a discrete current
sense approach. Figure 33 shows a more detailed
schematic of this approach. Droop is solved the same way
as the DCR sensing approach with a few slight
modifications.
First, because there is no NTC required for thermal
compensation, the R_n resistor network in the previous
section is not required. Second, because there is no time
constant matching required, the C_n component is not
matched to the L/DCR time constant. This component does
indeed provide noise immunity and therefore is populated
with a 39pF capacitor.
The R_S values in the previous section, R_S = 1.5k_1%, are
sufficient for this approach.
Now the input to the droop amplifier is essentially the
Vrsense voltage. This voltage is given by Equation 30.
Vrsense_EQV
=
R_{-----s---e---n----s---e-}
2
•
I_OUT
(EQ. 30)
The gain of the droop amplifier, K_droopamp, must be adjusted
for the ratio of the R_sense to droop impedance, R_droop. We
use the Equation 31.
K_droopamp
=
-^R----^d----^r--^o---^o---^p--
R_sense
•
2
(EQ. 31)
Solving for the R_drp2 value, R_droop = 0.0021(V/A) as per the
Intel IMVP-6+ specification, R_sense = 0.001Ω and
R_drp1 =1kΩ, we obtain in Equation 32.
R_drp2 = (K_droopamp – 1) • R_drp1= 3.2kΩ
(EQ. 32)
These values are extremely sensitive to layout. Once the
board has been laid out, some tweaking may be required to
adjust the full load droop. This is fairly easy and can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting R_drp2 to obtain the
desired droop value.
Fault Protection - Overcurrent Fault Setting
As previously described, the overcurrent protection of the
ISL6262A is related to the droop voltage. Previously we
have calculated that the droop voltage = ILoad*R_droop,
where R_droop is the load line slope specified as 0.0021 (V/A)
in the Intel IMVP-6+ specification. Knowing this relationship,
the overcurrent protection threshold can be set up as a
voltage droop level. Knowing this voltage droop level, one
can program in the appropriate drop across the R_OC
resistor. This voltage drop will be referred to as Voc. Once
the droop voltage is greater than Voc, the PWM drives will
turn off and PGOOD will go low.
The selection of R_OC is given in Equation 33. Assuming we
desire an overcurrent trip level, I_OC, of 55A, and knowing
from the Intel Specification that the load line slope, R_droop is
0.0021 (V/A), we can then calculate for R_OC as shown in
Equation 33.
R_OC
=
-^I-^O-----^C----₁-^•--₀--^R--_μ---^d-_A--^r---^o---^o---^p-
=
5_----5_-----•_----0_---._--0_---0_----2_---1_--
10 • 10^–6
=
11.5 k Ω
(EQ. 33)
Note: If the droop load line slope is not -0.0021 (V/A) in the
application, the overcurrent setpoint will differ from
predicted.
26
FN6343.1
December 23, 2008