ISL6262A Datasheet, PDF (18/28 Pages) Intersil Corporation – Two-Phase Core Controller Santa Rosa, IMVP-6+

ISL6262A
While PSI# is high, both phases are switching. If PSI# is
asserted low and either DPRSTP# or DPRSLPVR are not
asserted, the controller will transition to CCM operation with
only phase 1 switching, and both MOSFETs of phase 2 will
be off. The controller will thus eliminate switching losses
associated with the unneeded channel.
V_OUT AND V_SOFT
-2.5mV/µs
10mV/µs
DPRSLPVR
2.5mV/µs
VID #
For DPRSLPVR LOW, the large signal dV/dt will be
±10mV/s. As the output voltage approaches the VID
command value, the dV/dt moderates to prevent overshoot.
Keeping DPRSLPVR HIGH for voltage transitions into and
out of Deeper Sleep will result in low dV/dt output voltage
changes with resulting minimized audio noise. For fastest
recovery from Deeper Sleep to Active mode, holding
DPRSLPVR LOW results in maximum dV/dt. Therefore, the
ISL6262A is IMVP-6+ compliant for DPRSTP# and
DPRSLPVR logic.
Intersil's R³ Technology™ has intrinsic voltage feedforward.
As a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6262A will transiently raise
the switching frequency so that response time is decreased
and current is shared by two channels.
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
Protection
The ISL6262A provides overcurrent, overvoltage, under-
voltage protection and over-temperature protection as
shown in Table 3.
When PSI#, DPRSTP#, and DPRSLPVR are all asserted,
the controller will transition to single-phase DCM mode. In
this mode, both MOSFETs associated with phase 2 are off,
and the ISL6262A turns off the lower MOSFET of Channel 1
whenever the Channel 1 current decays to zero. As load is
further reduced, the phase 1 channel switching frequency
decreases to maintain high efficiency.
Dynamic Operation
See Figure 35. The ISL6262A responds to changes in VID
command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With C_SOFT = 15nF and DPRSLPVR HIGH, the output
voltage will move at ±2.8mV/s for large changes in voltage.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in
“Component Selection and Application” on page 19“. After
the load-line is set, the OCSET resistor can be selected to
detect overcurrent at any level of droop voltage. An
overcurrent fault will occur when the load current exceeds
the overcurrent setpoint voltage while the regulator is in a
2-phase mode. While the regulator is in a 1-phase mode of
operation, the overcurrent setpoint is automatically reduced
to 66% of two-phase overcurrent level. For overcurrents less
than 2.5 times the OCSET level, the over-load condition
must exist for 120µs in order to trip the OC fault latch. This is
shown in Figure 24.
Overcurrent fault
Way-Overcurrent fault
Overvoltage fault (1.7V)
Overvoltage fault (+200mV)
Undervoltage fault
(-300mV)
Unbalance fault
(7.5mV)
Over-temperature
fault (NTC <1.18V)
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6262A
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
120µs
PWM1, PWM2 three-state,
PGOOD latched low
<2µs
PWM1, PWM2 three-state,
PGOOD latched low
Immediately
Low-side MOSFET on until Vcore
<0.85V, then PWM three-state,
PGOOD latched low (OV to 1.7V
always)
1ms
PWM1, PWM2 three-state,
PGOOD latched low
1ms
PWM1, PWM2 three-state,
PGOOD latched low
1ms
PWM1, PWM2 three-state,
PGOOD latched low
Immediately
VR_TT# goes low
FAULT RESET
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
VR_ON toggle or VDD toggle
N/A
18
FN6343.1
December 23, 2008