ISL6262A Datasheet, PDF (23/28 Pages) Intersil Corporation – Two-Phase Core Controller Santa Rosa, IMVP-6+

ISL6262A
10µA
-
OC
+
INTERNAL TO
ISL6262A
+
1
+
-
OCSET
+
DROOP
-
VSUM
DFB
DROOP
VSUM
+
RSEQV
=
R_-----S_---
2
VdcrEQV
=
IOUT
× ^D-----^C-----^R---
2
VDIFF
+
1
+
-
Cn
VN
RTN VSEN
VO'
-
Rn
=
-⁽--^R-----ⁿ----^t--^c-----+-----^R-----^s----^e----^r--ⁱ--^e----^s----⁾----^×----^R-----^p----^a----^r-
(Rntc + Rseries) + Rpar
VO'
ROEQV
=
R_-----O_---
2
FIGURE 40. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DCR SENSING
thermistor should be placed in the spot which gives the best
indication of the temperature of voltage regulator circuit.
Static Mode of Operation - Static Droop Using DCR
Sensing
As previously mentioned, the ISL6262A has an internal
differential amplifier which provides for very accurate voltage
regulation at the die of the processor. The load line
regulation is also accurate for both two-phase and
single-phase operation. The process of selecting the
components for the appropriate load line droop is explained
here.
For DCR sensing, the process of compensation for DCR
resistance variation to achieve the desired load line droop
has several steps and is somewhat iterative.
The two-phase solution using DCR sensing is shown in
Figure 37. There are two resistors connecting to the terminals
of inductor of each phase. These are labeled R_S and R_O.
These resistors are used to obtain the DC voltage drop across
each inductor. Each inductor will have a certain level of DC
current flowing through it, and this current, when multiplied by
the DCR of the inductor, creates a small DC voltage drop
across the inductor terminal. When this voltage is summed with
the other channels DC voltages, the total DC load current can
be derived.
R_O is typically 1Ω to 10Ω. This resistor is used to tie the
outputs of all channels together and thus create a summed
average of the local CORE voltage output. R_S is determined
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the output of
each of these R_S resistors are tied together to create the
VSUM voltage node. With both the outputs of R_O and R_S tied
together, the simplified model for the droop circuit can be
derived. This is presented in Figure 40.
Figure 40 shows the simplified model of the droop circuitry.
Essentially one resistor can replace the R_O resistors of each
phase and one R_S resistor can replace the R_S resistors of
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by:
Equation 16.
V_{DCR_EQU}
=
-^I-^O-----^U----^T-----^•----^D-----^C-----^R--
2
(EQ. 16)
For the convenience of analysis, the NTC network
comprised of R_ntc, R_series and R_par, given in Figure 37, is
labeled as a single resistor R_n in Figure 40.
The first step in droop load line compensation is to adjust
R_n, RO_EQV and RS_EQV such that sufficient droop voltage
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb, we start with the voltage drop across the
R_n network, VN, to be 0.5 to 0.8 times V_{DCR_EQU}. This ratio
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 17.
R_n(T)
=
-⁽--^R-----^s---^e---^r--ⁱ--^e---^s----+-----^R-----ⁿ---^t--^c---⁾---^•-----^R----^p---^a----^r
R_series + R_ntc + R_par
(EQ. 17)
For simplicity, the gain of Vn to the V_{dcr_equ} is defined by
G1, also dependent on the temperature of the NTC
thermistor.
G₁(T)
Δ
=
--------------^R-----ⁿ---⁽---^T----⁾--------------
R_n(T) + RS_EQV
(EQ. 18)
DCR(T) = DCR_25°C • (1 + 0.00393*(T-25))
(EQ. 19)
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as shown in
Equation 20, where R_droop is the realized load line slope
and 0.00393 is the temperature coefficient of the copper.
23
FN6343.1
December 23, 2008