ISL6261 Datasheet, PDF (26/34 Pages) Intersil Corporation – Single-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
FIGURE 31. C4 ENTRY/EXIT, V_IN = 12.6V, Io = 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V, C4
VID = 0.7625V, FDE = DPRSLPVR,
Ch1: DPRSTP#, Ch2: Vo, Ch3: DPRSLPVR/FDE,
Ch4: PHASE
100A/us
FIGURE 32. VID TOGGLING, V_IN = 12.6V, Io= 0.7A,
HFM VID = 1.1V, LFM VID = 0.9V,
Ch1: SOFT, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
50A/us
FIGURE 33. LOAD STEP UP RESPONSE IN CCM,
V_IN = 8V, Io = 2AÆ20A at 100A/us, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
100A/us
50A/us
FIGURE 34. LOAD STEP DOWN RESPONSE IN CCM
V_IN = 8V, Io = 20AÆ2A at 100A/us, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
100A/us
50A/us
FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM
V_IN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
26
FIGURE 36. LOAD TRANSIENT RESPONSE IN ENHANCED
DEM, V_IN = 8V, Io = 2AÅÆ20A, VID = 1.1V,
Ch1: Io, Ch2: Vo, Ch3: Vcomp, Ch4: PHASE
FN9251.1
September 27, 2006