ISL6261 Datasheet, PDF (20/34 Pages) Intersil Corporation – Single-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6261
R_drp1 (R₁₁ in Figure 2) and R_drp2 (R₁₂ in Figure 2) sets the
droop amplifier gain, according to Equation 22:
k_droopamp
=1+
R_drp2
R _drp1
(EQ. 22)
After determining R_s and R_n networks, use Equation 23 to
calculate the droop resistances R_drp1 and R_drp2.
R_{drp 2}
=
(
R_droop
DCR ⋅ G1(25^o C)
− 1) ⋅ R_drp1
(EQ. 23)
R_droop is 2.1mV/A per lntel^® IMVP-6^® specification.
The effectiveness of the R_n network is sensitive to the
coupling coefficient between the NTC thermistor and the
inductor. The NTC thermistor should be placed in close
proximity of the inductor.
To verify whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current, and wait for the thermal steady state, and see how
much the output voltage deviates from the initial voltage
reading. Good thermal compensation can limit the drift to less
than 2mV. If the output voltage decreases when the
temperature increases, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Following the evaluation board value and layout of
NTC placement will minimize the engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated R_drp2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R_drp2 after the system
has achieved thermal equilibrium at full load. For example, if
the max current is 20A, one should apply 20A load current
and look for 42mV output voltage droop. If the voltage droop
is 40mV, the new value of R_dpr2 is calculated by:
R _{drp 2 _ new}
= ^{42 mV}
40 mV
( R _{drp 1} + R _{drp 2} ) − R _{drp 1}
(EQ. 24)
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. The
effective resistance on the VSUM pin is the parallel of R_s and
R_n, and the effective resistance on the DFB pin is the parallel
of R_drp1 and R_drp2.
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing
Figure 10 shows the desired waveforms during load
transient response. V_core needs to be as square as possible
at I_core change. The V_core response is determined by several
factors, namely the choice of output inductor and output
capacitor, the compensator design, and the droop capacitor
design.
The droop capacitor refers to C_n in Figure 9. If C_n is
designed correctly, its voltage will be a high-bandwidth
analog voltage of the inductor current. If C_n is not designed
correctly, its voltage will be distorted from the actual
waveform of the inductor current and worsen the transient
response. Figure 11 shows the transient response when C_n
is too small. V_core may sag excessively upon load
application to create a system failure. Figure 12 shows the
transient response when C_n is too large. V_core is sluggish in
drooping to its final value. There will be excessive overshoot
if a load occurs during this time, which may potentially hurt
the CPU reliability.
i_core
ΔI_core
V_core
V_core
ΔV_core
ΔV_core= ΔI_core×R_droop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
i_core
V_core
V_core
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO
SMALL
i_core
V_core
V_core
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C_n IS TOO
LARGE
The current sensing network consists of R_n, R_s and C_n. The
effective resistance is the parallel of R_n and R_s. The RC time
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform. Equation 25
shows this equation:
L
DCR
=
⎜⎜⎝⎛
R_n
R_n
×
+
R_s
R_s
⎟⎟⎠⎞ ^{× Cn}
(EQ. 25)
20
FN9251.1
September 27, 2006